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參數(shù)資料
| 型號(hào)： | IDT7028L |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 64K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 高速64K的× 16 DUAL-PORT靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 8/17頁(yè) |
| 文件大小： | 150K |
| 代理商： | IDT7028L |
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8
IDT7028L
High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
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W
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CE
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NOTES:
1. R/
W
or
CE
or
UB
and
LB
= V
IH
during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a
CE
= V
IL
and a R/
W
= V
IL
for memory array writing cycle.
3. t
WR
is measured fromthe earlier of
CE
or R/
W
(or
SEM
or R/
W
) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
or
SEM
= V
IL
transition occurs simultaneously with or after the R/
W
= V
IL
transition, the outputs remain in the High-impedance state.
6. Timng depends on which enable signal is asserted last,
CE
or R/
W
.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV fromsteady state with the Output Test Load
(Figure 2).
8. If
OE
= V
IL
during R/W controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t
DW
. If
OE
= V
IH
during an R/
W
controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t
WP
.
9. To access RAM
CE
= V
IL
and
SEM
= V
IH
. To access semaphore,
CE
= V
IH
and
SEM
= V
IL
. t
EW
must be met for either condition.
10. Refer to Chip Enable Truth Table.
R/
W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4)
(4)
(7)
UB
or
LB
4836 drw 07
(9)
CE
or
SEM
(9,10)
(7)
(3)
4836 drw 08
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/
W
t
AW
t
EW
UB
or
LB
(3)
(2)
(6)
CE
or
SEM
(9,10)
(9)
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