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參數(shù)資料
| 型號： | IDT7052 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2K x 8 FourPort STATIC RAM |
| 中文描述： | 高速2K × 8 FourPort靜態(tài)RAM |
| 文件頁數(shù)： | 8/11頁 |
| 文件大小： | 131K |
| 代理商： | IDT7052 |
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort Static RAM Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(7,8)
NOTES:
1. Transition is measured ±200mV fromLow or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. If
OE
= V
IL
during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers
to turn off data to be placed on the bus for the required t
DW
. If
OE
= V
IH
during an R/W controlled write cycle, this requirement
does not apply and the write pulse can be as short as the specified t
WP
. Specified for
OE
= V
IH
(refer to “Timng Waveformof Write Cycle”, Note 8).
4. Port-to-port delay through RAMcells fromwriting port to reading port, refer to “Timng Waveformof Write with Port-to-Port Read”.
5. To ensure that the write cycle is inhibited on port "A" during contention fromPort "B". Port "A" may be any of the four ports and Port "B" is any other port.
6. To ensure that a write cycle is completed on port "A" after contention fromPort "B". Port "A" may be any of the four ports and Port "B" is any other port.
7. 'X' in part number indicates power rating.
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7052X20
Com'l Only
7052X25
Com'l &
Mlitary
7052X35
Com'l &
Mlitary
Symbol
Parameter
Mn.
Max.
Mn.
Max.
Mn.
Max.
Unit
WRITE CYCLE
t
WC
Write Cycle Time
20
____
25
____
35
____
ns
t
EW
Chip Enable to End-of-Write
(3)
15
____
20
____
30
____
ns
t
AW
Address Valid to End-of-Write
15
____
20
____
30
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
(3)
15
____
20
____
30
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write
15
____
15
____
20
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
15
____
15
ns
t
DH
Data Hold Time
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
12
____
15
____
15
ns
t
OW
Output Active fromEnd-of-Write
(1,2)
0
____
0
____
0
____
ns
t
WDD
Write Pulse to Data Delay
(4)
____
35
____
45
____
55
ns
t
WDD
Write Data Valid to Read Data Delay
(4)
____
30
____
35
____
45
ns
BUSY
INPUT TIMING
t
WB
Write to
BUSY
(5)
0
____
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(6)
15
____
15
____
20
____
ns
2674 tbl 10
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| IDT7052L20PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 16KBIT 20NS 120TQFP |
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