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參數(shù)資料
| 型號(hào)： | IDT7052S |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2K x 8 FourPort STATIC RAM |
| 中文描述： | 高速2K × 8 FourPort靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大?。?/td> | 131K |
| 代理商： | IDT7052S |
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read
(1,2,3)
Functional Description
The IDT7052 provides four ports with separate control, address, and
I/O pins that permt independent access for reads or writes to any location
in memory. These devices have an automatic power down feature
controlled by
CE
. The
CE
controls on-chip power down circuitry that
permts the respective port to go into standby mode when not selected (
CE
= V
IH
). When a port is enabled, access to the entire memory array is
permtted. Each port has its own Output Enable control (
OE
). In the read
mode, the port’s
OE
turns on the output drivers when set LOW. READ/
WRITE conditions are illustrated in the table below.
Timing Waveform of Write with
BUSY
Input
NOTES:
1.
BUSY
is aserted on Port "B" blocking R/
W
"B"
until
BUSY
"B"
goes HIGH.
Truth Table I Read/Write Control
(3)
NOTES:
1. "H" = V
IH
, "L" = V
IL
, "X" = Dont Care, "Z "= High Impedance
2. If
BUSY
= V
IL
, write is blocked.
3. For valid write operation, no more than one port can write to the same address
location at the same time.
NOTES:
1. Assume
BUSY
input = V
IH
and
CE
= V
IL
for the writing port.
2.
OE
= V
IL
for the reading ports.
3. All timng is the same for left and right ports. Port "A" may be either of the four ports and Port
"B" is any other port.
2674 drw 11
ADDR
"A"
t
WC
DATA
"B"
MATCH
t
WP
R/
W
"A"
DATA
IN"A"
ADDR
"B"
t
DH
VALID
MATCH
VALID
t
DDD
t
WDD
t
DW
2674 drw 12
R/
W
"A"
BUSY
"B"
t
WP
t
WH
t
WB
R/
W
"B"
(1)
,
Any Port
(1)
R/
W
CE
OE
D
0-7
Function
X
H
X
Z
Port Deselected: Power-Down
X
H
X
Z
CE
P1
=
CE
P2
=
CE
P3
=
CE
P4
=V
IH
Power Down Mode I
SB
or I
SB1
L
L
X
DATA
IN
Data on port written into memory
(2)
H
L
L
DATA
OUT
Data in memory output on port
X
X
H
Z
Outputs Disabled
2674 tbl 11
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