參數(shù)資料
型號(hào): IDT7052S
廠商: Integrated Device Technology, Inc.
英文描述: HIGH-SPEED 2K x 8 FourPort STATIC RAM
中文描述: 高速2K × 8 FourPort靜態(tài)RAM
文件頁數(shù): 7/11頁
文件大?。?/td> 131K
代理商: IDT7052S
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort Static RAM Military, Industrial and Commercial Temperature Ranges
2674 drw 08
t
AOE
t
LZ
t
HZ
DATA
OUT
CE
t
ACE
VALID DATA
OE
CURRENT
I
CC
I
SB
t
PU
50%
t
LZ
t
PD
50%
t
HZ
2674 drw 07
t
AA
t
OH
t
OH
DATA
OUT
ADDRESS
t
RC
DATA VALID
PREVIOUS DATA VALID
Timing Waveform of Read Cycle No. 1, Any Port
(1)
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(3,4)
NOTES:
1. Transition is measured ±200mV fromLow or High-Impedance voltage with the Output Test Load (Figure 2)
2. This parameter is guaranteed by device characterization but is not production tested.
3. 'X' in part number indicates power rating (S or L)
4. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Timing Waveform of Read Cycle No. 2, Any Port
(1,2)
NOTES:
1. R/
W
= V
IH
,
OE
= V
IL
and
CE
= V
IL.
NOTES:
1. R/
W
= V
IH
for Read Cycles.
2. Addresses valid prior to or coincident with
CE
transition LOW.
7052X20
Com'l Only
7052X25
Com'l &
Mlitary
7052X35
Com'l &
Mlitary
Symbol
Parameter
Mn.
Max.
Mn.
Max.
Mn.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
20
____
25
____
35
____
ns
t
AA
Address Access Time
____
20
____
25
____
35
ns
t
ACE
Chip Enable Access Time
____
20
____
25
____
35
ns
t
AOE
Output Enable Access Time
____
10
____
15
____
25
ns
t
OH
Output Hold fromAddress Change
0
____
0
____
0
____
ns
t
LZ
Output Low-Z Time
(1,2)
5
____
5
____
5
____
ns
t
HZ
Output High-Z Time
(1,2)
____
12
____
15
.____
15
ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
20
____
25
____
35
ns
2674 tbl 09
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