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參數(shù)資料
| 型號： | IDT707278L25PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Low-Noise JFET-Input Operational Amplifier 8-SOIC 0 to 70 |
| 中文描述： | 32K X 16 DUAL-PORT SRAM, 25 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 135K |
| 代理商： | IDT707278L25PFI |
6.42
IDT707278S/L
32K x 16 Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
The IDT707278 is a high-speed 32K x 16 (512K bit) Bank-Switchable
Dual-Ported SRAMorganized into four independent 8K x 16 banks. The
device has two independent ports with separate controls, addresses, and
I/O pins for each port, allowing each port to asynchronously access any
8K x 16 memory block not already accessed by the other port. Accesses
by the ports into specific banks are controlled via bank select pin inputs
under the user's control. Mailboxes are provided to allow inter-processor
communications. Interrupts are provided to indicate mailbox writes have
occurred. An automatic power down feature controlled by the chip enables
(
CE
0
and CE
1
) permts the on-chip circuitry of each port to enter a very
low standby power mode and allows fast depth expansion.
The IDT707278 offers a maximumaddress-to-data access time as fast
as 15ns, and is packaged in a 100-pin Thin Quad Flatpack (TQFP).
The IDT707278 is a high-speed asynchronous 32K x 16 Bank-
Switchable Dual-Ported SRAM organized in four 8K x 16 banks. The two
ports are permtted independent, simultaneous access into separate banks
within the shared array. There are four user-controlled Bank Select input
pins, and each of these pins is associated with a specific bank within the
memory array. Access to a specific bank is gained by placing the
associated Bank Select pin in the appropriate state: V
IH
assigns the bank
to the left port, and V
IL
assigns the bank to the right port (See Truth Table
IV). Once a bank is assigned to a particular port, the port has full access
to read and write within that bank. Each port can be assigned as many
banks within the array as needed, up to and including all four banks.
The IDT707278 provides mailboxes to allow inter-processor commu-
nications. Each port has four 16-bit mailbox registers available to which
it can write and read and which the opposite port can read only. These
mailboxes are external to the common SRAMarray, and are accessed
by setting
MBSEL
= V
IL
while setting
CE
= V
IH
. Each mailbox has an
associated interrupt: a port can generate an interrupt to the opposite port
by writing to the upper byte of any one of its four 16-bit mailboxes. The
interrupted port can clear the interrupt by reading the upper byte. This read
will not alter the contents of the mailbox.
If desired, any source of interrupt can be independently masked via
software. Two registers are provided to permt interpretation of interrupts:
the Interrupt Cause Register and the Interrupt Status Register. The
Interrupt Cause Register gives the user a snapshot of what has caused
the interrupt to be generated - the specific mailbox written to. The
information in this register provides post-mask signals: Interrupt sources
that have been masked will not be updated. The Interrupt Status Register
gives the user the status of all bits that could potentially cause an interrupt
regardless of whether they have been masked. Truth Table V gives a
detailed explanation of the use of these registers.
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