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參數(shù)資料
| 型號(hào)： | IDT70824S35PFB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM⑩) |
| 中文描述： | 4K X 16 STANDARD SRAM, 35 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 205K |
| 代理商： | IDT70824S35PFB |
10
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory Military and Commercial Temperature Ranges
End of buffer flag for Buffer #1
End of buffer flag for Buffer #2
15
0
MSB
H
H
H
H
H
H
H
H
H
H
H
H
H
1
0
LSB I/O BITS
H
3099 drw 12
9#E"6#!
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.
D"$#
#
>
,!
NOTES:
1. "H" = V
OH
for I/O in the output state and "Don't Cares"' for I/O in the input state.
2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs asynchronously
of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled by
CNTEN
. The pointer is
also released by
RST
,
SLD
,
SSTRT
1
and
SSTRT
2
operations.
>
!
NOTE:
1. "H" = V
OH
for I/O in the output state and "Don't Cares" for I/O in the input state.
B#D"$
!
NOTES:
1.
EOB
1
and
EOB
2
may be asserted (set) at the same time, if both end addresses have been loaded with the same value.
2.
CMD
flow control bits are unchanged, the count does not continue advancement.
3. If
EOB
1
and
EOB
2
are equal, then the pointer will jump to the start of Buffer #1.
4. If the counter has stopped at
EOB
x and was released by bit 4 of the flow control register,
CNTEN
must be LOW on the next rising edge of SCLK; otherwise the flow
control will remain in the stop mode.
5. Flow Control Bit settings of '10' and '11' are reserved.
6. Start address and End of address for Buffer #2 and the Flow Control for both Buffer #1 and #2, must be programmed as described in the "Buffer Command Mode"
section.
RST
conditions are not set to valid addresses.
B"$
A#
!
NOTES:
1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be
cleared while the second is left alone, or both may be cleared.
2. Remains as it was prior to the
CMD
operation, either HIGH (1) or LOW (0).
Buffer #1 flow control
Buffer #2 flow control
Counter Release
(STOP Mode Only)
15
MSB
LSB I/O BITS
0
H
H
H
H
H
H
H
4
3
2
1
0
H
H
H
H
3099 drw 11
Flow Control
Bit 1 & Bit 0
(Bit 3 & Bit 2)
Mode
Functional Description
00
BUFFER
CHAINING
EOB
1
(
EOB
2
) is asserted (Active LOW output) when the pointer matches the end address of Buffer #1 (Buffer #2).
The pointer value is changed to the start address of Buffer #2 (Buffer #1)
(1,3)
01
STOP
EOB
1
(
EOB
2
) is asserted when the pointer matches the end address of Butler #1 (Butler #2).
The address pointer wll stop incrementing when it reaches the next address
(EO
B address + 1), if
CNTEN
is LOW
on the next clock's rising edge. Otherwise, the address pointer will stop incrementing on
EOB
. Sequential write
operations are inhibited after the address pointer is stopped. The pointer can be released by bit 4 of the flow
control register
(1,2,4)
3099 tbl 17
Flag Status Bit 0, (Bit 1)
Functional Description
0
Clears Buffer Flag
EOB
1
, (
EOB
2
).
1
No change to the Buffer Flag.
(2)
3099 tbl 18
Flag Status Bit 0, (Bit 1)
Functional Description
0
EOB
1
(
EOB
2
) flag has not been set, the
Pointer has not reached the End of the
Buffer
1
EOB
1
(
EOB
2
) flag has been set, the
Pointer has reached the end of the
Buffer
3099 tbl 19
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