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參數(shù)資料
| 型號： | IDT70824S45PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM⑩) |
| 中文描述： | 4K X 16 STANDARD SRAM, 45 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 205K |
| 代理商： | IDT70824S45PF |
8
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory Military and Commercial Temperature Ranges
)/)&"$%##3
C,!
$%###
!
NOTE:
1. "H" = V
IH
and "L" = V
IL
for the SI/O intput state.
NOTE:
1. At SCLK edge (A), SI/O
0
-SI/O
11
data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e.
address pointer changes). At SCLK edge (A),
SSTRT
1
and
SSTRT
2
must be HIGH to ensure for proper sequential address pointer loading. At SCLK edge (B),
SLD
and
SSTRT
1,2
must be HIGH to ensure for proper sequential address pointer loading. For
SSTRT
1
or
SSTRT
2
, the data to be read will be ready for edge
(B), while data will not be ready at edge (B) when
SLD
is used, but will be ready at edge (C).
SLD
'#
!
###
In
SLD
mode, there is an internal delay of one cycle before the address
pointer changes in the cycle following
SLD
. When
SLD
is LOW, data on
the inputs SI/O
0
-SI/O
11
is loaded into a data-in register on the LOW-to-
HIGH transition of SCLK. On the cycle following
SLD
, the address pointer
SLD
!
changes to the address location contained in the data-in register.
SSTRT
1
,
SSTRT
2
may not be low while
SLD
is LOW, or during the cycle following
SLD
. The
SSTRT
1
and
SSTRT
2
require only one clock cycle, since these
addresses are pre-loaded in the registers already.
NOTES:
1. H = V
IH
, L = V
IL
, X = Don't Care, and High-Z = High-impedance.
2.
RST
is continuously HIGH. The conditions of
SCE
CNTEN
, and SR/
W
are unrelated to the sequential address pointer operations.
3.
CE
,
OE
, R/
W
,
LB
,
UB
, and I/O
0
-I/O
15
are unrelated to the sequential port control and operation, except for
CMD
which must not be used concurrently with the sequential
port operation (due to the counter and register control).
CMD
should be HIGH (
CMD
= V
IH
) during sequential port access.
4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.
5. When
SLD
is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of
CNTEN
is ignored and the address is not incremented
during the two cycles.
6.
SOE
may be LOW with
SCE
deselect or in the write mode using SR/
W
.
Inputs/Outputs
MODE
SCLK
SLD
SSTRT
1
SSTRT
1
SOE
↑
H
L
H
X
Non-Counter Advanced Sequential Write, wthout
EOB
1
or
EOB
2
reached.
↑
H
H
L
X
Counter Advanced Sequential Write with
EOB
1
and
EOB
2
reached.
↑
L
H
H
H
(6)
No Write or Read due to Sequential port Deselect. No counter advance.
3099 tbl 14
SLD
SCLK
SI/O
0-11
SSTRT
(1 or 2)
A
B
ADDR
IN
3099 drw 08
C
DATA
OUT
(1)
15
MSB
LSB SI/O BITS
3099 drw 09
H
H
11 --------------------------------------------------------------------------------------------------
Address Loaded into Pointer
0
14
13
H
L
12
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