參數(shù)資料
型號(hào): IDT70V27L25BF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM
中文描述: 32K X 16 DUAL-PORT SRAM, 25 ns, PBGA144
封裝: 12 X 12 MM, 1.40 MM HEIGHT, FBGA-144
文件頁(yè)數(shù): 12/22頁(yè)
文件大?。?/td> 192K
代理商: IDT70V27L25BF
Commercial and Industrial Temperature Range
W
-'
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
'/: /;&".
12
!"4"D$
NOTES:
1. R/
W
or
CE
or
UB
and
LB
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a LOW
CE
and a LOW R/
W
for memory array writing cycle.
3. t
WR
is measured fromthe earlier of
CE
or R/
W
(or
SEM
or R/
W
) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
or
SEM
LOW transition occurs simultaneously with or after the R/
W
LOW transition, the outputs remain in the High-impedance state.
6. Timng depends on which enable signal is asserted last,
CE
or R/
W
.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV fromsteady state with the Output Test Load (Figure
2).
8. If
OE
is LOW during R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off and data to be placed
on the bus for the required t
DW
. If
OE
is HIGH during an R/
W
controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t
WP
.
9. To access RAM
CE
= V
IL
and
SEM
= V
IH
. To access semaphore,
CE
= V
IH
and
SEM
= V
IL
. t
EW
must be met for either condition.
10. Refer to Chip Enable Truth Table.
'/: /;&"
CE
"
UB
"
LB
-'
!"4$
R/
W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4)
(4)
(7)
UB
or
LB
3603 drw 07
(9)
CE
or
SEM
(9,10)
(7)
(3)
3603 drw 08
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/
W
t
AW
t
EW
UB
or
LB
(3)
(2)
(6)
CE
or
SEM
(9,10)
(9)
相關(guān)PDF資料
PDF描述
IDT70V27L25BFI HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM
IDT70V27L25G HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM
IDT70V27L25GI HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM
IDT70V27L25PF HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM
IDT70V27L25PFI HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT70V27L25PF 功能描述:IC SRAM 512KBIT 25NS 100TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 雙端口,同步 存儲(chǔ)容量:1.125M(32K x 36) 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA(17x17) 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8
IDT70V27L25PF8 功能描述:IC SRAM 512KBIT 25NS 100TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 雙端口,同步 存儲(chǔ)容量:1.125M(32K x 36) 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA(17x17) 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8
IDT70V27L35PF 功能描述:IC SRAM 512KBIT 35NS 100TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 雙端口,同步 存儲(chǔ)容量:1.125M(32K x 36) 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA(17x17) 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8
IDT70V27L35PF8 功能描述:IC SRAM 512KBIT 35NS 100TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 雙端口,同步 存儲(chǔ)容量:1.125M(32K x 36) 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA(17x17) 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8
IDT70V27L35PFI 功能描述:IC SRAM 512KBIT 35NS 100TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類(lèi)型:EEPROM 存儲(chǔ)容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?(單線) 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP,8-MSOP(0.118",3.00mm 寬) 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR)