參數(shù)資料
型號(hào): IDT70V639S15BF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
中文描述: 128K X 18 DUAL-PORT SRAM, 15 ns, PBGA208
封裝: 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-208
文件頁(yè)數(shù): 13/23頁(yè)
文件大?。?/td> 187K
代理商: IDT70V639S15BF
IDT70V639S
High-Speed 3.3V 128K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Preliminary
13
&.A0'+,.&'0,
"
NOTES:
1. D
OR
= D
OL
= V
IL
,
CE
L
=
CE
R
= V
IH
. Refer also to Truth Table II for appropriate
UB
/
LB
controls.
2. All timng is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite fromport "A".
3. This parameter is measured fromR/
W
"A"
or
SEM
"A"
going HIGH to R/
W
"B"
or
SEM
"B"
going HIGH.
4. If t
SPS
is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
&.A0'.
!"
NOTES:
1.
CE
= V
IH
or
UB
and
LB
= V
IH
for the duration of the above timng (both write and read cycle) (Refer to Chip Enable Truth Table). Refer also to Truth Table II for appropriate
UB
/
LB
controls.
2. "DATA
OUT
VALID" represents all I/O's (I/O
0
- I/O
17
) equal to the semaphore value.
SEM
/
UB
/
LB
(1)
5621 drw 10
t
AW
t
EW
I/O
VALID ADDRESS
t
SAA
R/
W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
VALID
IN
DATA
OUT
VALID
(2)
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
Read Cycle
Write Cycle
A
0
-A
2
OE
t
SOP
t
SOP
SEM
"A"
5621 drw 11
t
SPS
MATCH
R/
W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE
"A"
(2)
SEM
"B"
R/
W
"B"
A
0"B"
-A
2"B"
SIDE
"B"
(2)
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