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參數(shù)資料
| 型號(hào)： | IDT70V9279S9PRF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 32K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM |
| 中文描述： | 32K X 16 DUAL-PORT SRAM, 20 ns, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 337K |
| 代理商： | IDT70V9279S9PRF |
6.42
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance
(1)
15
Timing Waveform of Flow-Through Read with Address Counter Advance
(1)
NOTES:
1.
CE
0
,
OE
,
UB
, and
LB
= V
IL
; CE
1
, R/
W
, and
CNTRST
= V
IH
.
2. If there is no address change via
ADS
= V
IL
(loading a new address) or
CNTEN
= V
IL
(advancing the address), i.e.
ADS
= V
IH
and
CNTEN
= V
IH
, then the data
output remains constant for subsequent clocks.
ADDRESS
An
CLK
DATA
OUT
Qx - 1
(2)
Qx
Qn
Qn + 2
(2)
Qn + 3
ADS
CNTEN
t
CYC2
t
CH2
t
CL2
3743 drw 14
t
SA
t
HA
t
SAD
t
HAD
t
CD2
t
DC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
t
SAD
t
HAD
t
SCN
t
HCN
READ
WITH
COUNTER
Qn + 1
ADDRESS
An
CLK
DATA
OUT
Qx
(2)
Qn
Qn + 1
Qn + 2
Qn + 3
(2)
Qn + 4
ADS
CNTEN
t
CYC1
t
CH1
t
CL1
t
SA
t
HA
t
SAD
t
HAD
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
t
CD1
t
DC
t
SAD
t
HAD
t
SCN
t
HCN
READ
WITH
COUNTER
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