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參數(shù)資料
| 型號： | IDT7130LA20JB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Dual UART with 16-Byte FIFOs & Parallel Port 68-PLCC 0 to 70 |
| 中文描述： | 高速每1000 × 8雙端口靜態(tài)RAM |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 218K |
| 代理商： | IDT7130LA20JB |
6.01
7
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
(3)
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(5)
7130X20
(2)
7130X25
(6)
7140X25
(6)
Min. Max.
7130X35
7140X35
Min.
7130X55
7140X55
7130X100
7140X100
Min.
Symbol
Write Cycle
t
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
t
HZ
t
DH
t
WZ
t
OW
NOTES:
1. Transition is measured
±
500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. 0
°
C to +70
°
C temperature range only, PLCC and TQFP packages.
3. For MASTER/SLAVE combination, t
WC
= t
BAA
+ t
WP
, since R/
W
= V
IL
must occur after t
BAA.
4. If
OE
is low during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off
data to be placed on the bus for the required t
DW
. If
OE
is High during a R/
W
controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t
WP
.
5. “X” in part numbers indicates power rating (SA or LA).
6. Not available in DIP packages.
Parameter
Min.
Max.
Max. Min.
Max.
Max.
Unit
Write Cycle Time
(3)
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
(4)
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time
(1)
Data Hold Time
Write Enabled to Output in High-Z
(1)
Output Active From End-of-Write
(1)
20
15
15
0
15
0
10
—
0
—
0
—
—
—
—
—
—
—
10
—
10
—
25
20
20
0
15
0
12
—
0
—
0
—
—
—
—
—
—
—
10
—
10
—
35
30
30
0
25
0
15
—
0
—
0
—
—
—
—
—
—
—
15
—
15
—
55
40
40
0
30
0
20
—
0
—
0
—
—
—
—
—
—
—
25
—
25
—
100
90
90
0
55
0
40
—
0
—
0
—
—
—
—
—
—
—
40
—
40
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2689 tbl 10
t
ACE
t
AOE
t
HZ
t
LZ
t
PD
VALID DATA
t
PU
50%
DATA
OUT
CURRENT
I
CC
I
SS
50%
2689 drw 09
(4)
(1)
(1)
(2)
(2)
(4)
t
LZ
t
HZ
NOTES:
1. Timing depends on which signal is asserted last,
OE
or
CE
.
2. Timing depends on which signal is deaserted first,
OE
or
CE
.
3. R/
= V
IH
and the address is valid prior to or coincidental with
CE
transition Low.
4. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
, t
AA
, and t
BDD
.
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