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參數(shù)資料
| 型號： | IDT7130LA20JB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Dual UART with 16-Byte FIFOs & Parallel Port 68-PLCC 0 to 70 |
| 中文描述： | 高速每1000 × 8雙端口靜態(tài)RAM |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 218K |
| 代理商： | IDT7130LA20JB |
6.01
9
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(7)
8
M824S258M824S30
7132158M824S4
7130X100
7140X100
Max.
7130X20
(1)
7130X25
(9)
7140X25
(9)
Min. Max. Min. Max.
7130X35
7140X35
7130X55
7140X55
Min. Max. Min.
Symbol
Busy Timing (For Master lDT7130 Only)
t
BAA
BUSY
Access Time from Address
t
BDA
BUSY
Disable Time from Address
t
BAC
BUSY
Access Time from Chip Enable
t
BDC
BUSY
Disable Time from Chip Enable
t
WH
Write Hold After
BUSY
(6)
t
WDD
Write Pulse to Data Delay
(2)
t
DDD
Write Data Valid to Read Data Delay
(2)
t
APS
Arbitration Priority Set-up Time
(3)
t
BDD
BUSY
Disable to Valid Data
(4)
Busy Timing (For Slave IDT7140 Only)
e
t
WB
Write to
BUSY
Input
(5)
t
WH
Write Hold After
BUSY
(6)
t
WDD
Write Pulse to Data Delay
(2)
t
DDD
Write Data Valid to Read Data Delay
(2)
Parameter
Min. Max.
Unit
—
—
—
—
12
—
—
5
—
5
0
12
—
—
20
20
20
20
—
40
30
—
25
—
—
—
40
30
—
—
—
—
15
—
—
5
—
5
0
15
—
—
20
20
20
20
—
50
35
—
35
—
—
—
50
35
—
—
—
—
20
—
—
5
—
5
0
20
—
—
20
20
20
20
—
60
35
—
35
—
—
—
60
35
—
—
—
—
20
—
—
5
—
5
0
20
—
—
30
30
30
30
—
80
55
—
50
—
—
—
80
55
—
—
—
—
20
—
—
5
—
5
0
20
—
—
50
50
50
50
—
120
100
—
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
120
100
ns
ns
ns
ns
NOTES:
1. Com'l Only, 0
°
C to +70
°
C temperature range. PLCC and TQFP packages only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and
BUSY
."
3. To ensure that the earlier of the two ports wins.
4. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual), or t
DDD
– t
DW
(actual).
5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. “X” in part numbers indicates power rating (SA or LA).
8. Not available in DIP packages.
2689 tbl 11
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND
BUSY
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
’B’
DATA
OUT’B’
DATA
IN’A’
ADDR
’A’
MATCH
VALID
MATCH
VALID
R/
W
’A’
BUSY
’B’
t
APS
2689 drw 12
(1)
NOTES:
1. To ensure that the earlier of the two ports wins.
t
BDD
is ignored for slave (IDT7140).
2.
CE
L
=
CE
R
= V
IL.
3. OE = V
IL
for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
(2,3,4)
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