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參數(shù)資料
| 型號： | IDT7132LA100C |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS |
| 中文描述： | 2K X 8 DUAL-PORT SRAM, 100 ns, CDIP48 |
| 封裝： | 0.620 X 2.430 INCH, 0.150 INCH HEIGHT, SIDE BRAZED, DIP-48 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 255K |
| 代理商： | IDT7132LA100C |
12
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and
BUSY
(2,3,4)
Timing Waveform of Write with
BUSY
(4)
NOTES:
1.
2.
3.
4.
t
WH
must be met for both
BUSY
Input (IDT7142, slave) or Output (IDT7132, master).
BUSY
is asserted on port "B" blocking R/
W
"B"
, until
BUSY
"B"
goes HIGH.
t
WB
applies only to the slave version (IDT7142).
All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
BUSY
"B"
2692 drw 12
R/
W
"A"
t
WP
t
WH
(1)
t
WB
R/
W
"B"
(2)
(3)
,
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
"B"
DATA
OUT"B"
DATA
IN"A"
ADDR
"A"
MATCH
VALID
MATCH
VALID
R/
W
"A"
BUSY
"B"
t
APS
(1)
2692 drw 11
t
BAA
NOTES:
1.
2.
3.
4.
To ensure that the earlier of the two ports wins.
t
APS
is ignored for Slave (IDT7142).
CE
L
=
CE
R
= V
IL
OE
= V
IL
for the reading port.
All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
發(fā)布緊急采購，3分鐘左右您將得到回復。