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參數(shù)資料
| 型號(hào)： | IDT7187S35L22B |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS STATIC RAM 64K (64K x 1-BIT) |
| 中文描述： | 64K X 1 STANDARD SRAM, 35 ns, CQCC22 |
| 封裝： | LCC-22 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大?。?/td> | 70K |
| 代理商： | IDT7187S35L22B |
6.2
6
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT)
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1
(1,2)
TIMING WAVEFORM OF READ CYCLE NO. 2
(1,3)
NOTES:
1.
WE
is HIGH for Read cycle.
2.
CS
is LOW for Read cycle.
3. Address valid prior to or coincident with
CS
transition LOW.
4. Transition is measured
±
200mV from steady state voltage with specified loading in Figure 2.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
2986 drw 07
ADDRESS
DATA
t
RC
t
AA
OUT
t
OH
PREVIOUS DATA VALID
DATA VALID
(5)
2986 drw 08
DATA
OUT
CS
t
ACS
(4)
t
LZ
(4)
HZ
t
t
PD
t
PU
I
CC
I
SB
SUPPLY
CURRENT
V
CC
t
RC(5)
HIGH
IMPEDANCE
DATA VALID
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
7187S25
7187L25
Min. Max. Min.
7187S35/45
(1)
7187L35/45
(1)
7187S55
(1)
7187L55
(1)
7187S70
(1)
7187L70
(1)
Min. Max.
7187S85
(1)
7187L85
(1)
Min. Max. Unit
Symbol
Parameter
Max. Min. Max.
Write Cycle
t
WC
Write Cycle Time
25
—
35/45
—
55
—
70
—
85
—
ns
t
CW
Chip Select to End-of-Write
20
—
25/40
—
50
—
55
—
65
—
ns
t
AW
Address Valid to End-of-Write
20
—
25/40
—
50
—
55
—
65
—
ns
t
AS
Address Set-up Time
0
—
0
—
0
—
0
—
0
—
ns
t
WP
Write Pulse Width
20
—
20/25
—
35
—
40
—
45
—
ns
t
WR
Write Recovery Time
0
—
0
—
0
—
0
—
0
—
ns
t
DW
Data Valid to End-of-Write
15
—
15/25
—
25
—
30
—
35
—
ns
t
DH
t
WZ(2)
t
OW(2)
Data Hold Time
5
—
5
—
5
—
5
—
5
—
ns
Write Enable to Output in High-Z
—
12
—
15/30
—
30
—
30
—
40
ns
Output Active from End-of-Write
0
—
0
—
0
—
0
—
0
—
ns
NOTES:
1. –55
°
C to +125
°
C temperature range only.
2. This parameter guaranteed but not tested.
2986 tbl 12
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