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參數(shù)資料
| 型號： | IDT7188S35DB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS STATIC RAM 64K 16K x 4-BIT |
| 中文描述： | 16K X 4 STANDARD SRAM, 35 ns, CDIP22 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-22 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 88K |
| 代理商： | IDT7188S35DB |
4
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
Data Retention Characteristics
(L Version Only) (V
HC
= V
CC
- 0.2V)
Low V
CC
Data Retention Waveform
AC Test Conditions
Input Pulse Levels
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
HZ
, t
LZ
, t
WZ
, t
OHZ
and t
OW
)
*Includes scope and jig capacitances
2989 drw 03
DATA
RETENTION
MODE
4.5V
4.5V
V
DR
≥
2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS
V
DR
,
2989 drw 04
480
30pF*
255
DATA
OUT
5V
,
2989 drw 05
480
5pF*
255
DATA
OUT
5V
,
NOTES:
1. T
A
= +25°C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
Typ.
(1)
V
CC
@
Max.
V
CC
@
Symbol
Parameter
Test
Condition
Mn.
2.0V
3.0V
2.0V
3.0V
Unit
V
DR
V
CC
for Data Retention
____
2.0
____
____
____
____
V
I
CCDR
Data Retention Current
____
10
15
600
900
μ
A
t
CDR
(3)
Chip Deselect to Data Retention Time
CS
> V
HC
V
IN
> V
HC
or
< V
LC
0
____
____
____
____
ns
t
R
(3)
Operation Recovery Time
t
RC
(2)
____
____
____
____
ns
I
I
LI
I
(3)
Input Leakage Current
____
____
____
2
2
μ
A
2989 tbl 09
Input Rise/Fall Times
Input Timng Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2989 tbl 10
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相關代理商/技術參數(shù) |
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|---|---|
| IDT7188S35P | 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT7198S35P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT7198S85LB | 制造商:IDT 功能描述:IC |
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