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參數(shù)資料
| 型號： | IDT7188S45DB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS STATIC RAM 64K 16K x 4-BIT |
| 中文描述： | 16K X 4 STANDARD SRAM, 45 ns, CDIP22 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-22 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 88K |
| 代理商： | IDT7188S45DB |
6.42
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
5
Timing Waveform of Read Cycle No. 2
(1,3)
NOTES:
1.
WE
is HIGH for Read cycle.
2.
CS
is LOW for Read cycle.
3. Address valid prior to or coincident with
CS
transition LOW.
4. Transition is measured ±200mV fromsteady state voltage.
5. All Read cycle timngs are referenced fromthe last valid address to the first transitioning address.
Timing Waveform of Read Cycle No. 1
(1,2)
AC Electrical Characteristics
(V
CC
= 5.0V ± 10%)
ADDRESS
DATA
OUT
2989 drw 06
t
RC
t
AA
t
OH
PREVIOUS DATA VALID
DATA VALID
(5)
,
DATA
OUT
CS
I
CC
I
SB
V
CC
SUPPLY
CURRENT
2989 drw 07
t
ACS
(4)
t
LZ
(4)
t
HZ
t
PD
t
PU
(5)
t
RC
DATA VALID
HIGH IMPEDANCE
,
NOTE:
1. This parameter is guaranteed by device characterization but is not production tested.
Symbol
Parameter
7188S25
7188L25
7188S35
7188L35
7188S45
7188L45
7188S55
7188L55
7188S70
7188L70
7188S85
7188L85
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
25
____
35
—
45
—
55
____
70
____
85
____
ns
t
AA
Address Access Time
____
25
____
35
____
45
____
55
____
70
____
85
ns
t
ACS
Chip Select Access Time
____
25
____
35
____
45
____
55
____
70
____
85
ns
t
OH
Output Hold fromAddress Change
5
____
5
____
5
____
5
____
5
____
5
____
ns
t
LZ
(1)
Output Select to Output in Low-Z
5
____
5
____
5
____
5
____
5
____
5
____
ns
t
HZ
(1)
Chip Deselect to Output in High-Z
____
10
____
14
____
14
____
20
____
25
____
30
ns
t
PU
(1)
Chip Select to Power Up Time
0
____
0
____
0
____
0
____
0
____
0
____
ns
t
PD
(1)
Chip Deselect to Power Down Time
____
25
____
35
____
45
____
55
____
70
____
85
ns
2989 tbl 11
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