參數(shù)資料
型號: IDT71P74204S250BQ
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 18Mb Pipelined QDR II SRAM Burst of 4
中文描述: 2M X 8 QDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁數(shù): 15/22頁
文件大?。?/td> 592K
代理商: IDT71P74204S250BQ
6.42
15
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information
18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry
when in test mode. This is to support connectivity testing during manufacturing and systemdiagnostics. In conformance with IEEE 1149.1, the
SRAMcontains a TAP controller Instruction register, Bypass Register and ID register The TAP controller has a standard 16-state machine that
resets internally upon power-up; therefore, the TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable
the TAP controller without interfacing with normal operation of the SRAM TCK must be tied to VSS to preclude a md level input. TMS and TDI
are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a register. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2
IR1
IR0
Instruction
TDO Output
Notes
0
0
0
EXTEST
Boundary Scan Register
0
0
1
IDCODE
Identification register
2
0
1
0
SAMPLE-Z
Boundary Scan Register
1
0
1
1
RESERVED
Do Not Use
5
1
0
0
SAMPLE/PRELOAD Boundary Scan register
4
1
0
1
RESERVED
Do Not Use
5
1
1
0
RESERVED
Do Not Use
5
1
1
1
BYPASS
Bypass Register
3
6111tbl 13
NOTES:
1. Places Qs in Hi-Z in order to sample all input data regardless of
other SRAMinputs.
2. TDI is sampled as an input to the first ID register to allow for the
serial shift of the external TDI data.
3. Bypass register is initialized to Vss when BYPASS instruction is
invoked. The Bypass Register also holds serially loaded TDI when
existing the Shift DR states.
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
TAP Controller State Diagram
Test Logic Reset
Run Test Idle
Select DR
Capture DR
Pause DR
Exit 2 DR
Update DR
Shift DR
Exit 1 DR
Select IR
Capture IR
Pause IR
Exit 2 IR
Update IR
Shift IR
Exit 1 IR
0
0
0
0
0
0
1
1
1
1
1
1
1
0
6111 drw 17
0
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg
.
Control Signal
s
TAP Controller
A,D
K,
K
C,C
Q
CQ
CQ
TDI
TMS
TCK
TDO
6111drw18
S
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IDT71P74604S167BQ8 功能描述:IC SRAM 18MBIT 167MHZ 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M(1M x 8,512K x 16) 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA(7x7) 包裝:托盤
IDT71P74604S167BQG 功能描述:IC SRAM 18MBIT 167MHZ 165FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M(1M x 8,512K x 16) 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA(7x7) 包裝:托盤
IDT71P74604S167BQG8 功能描述:IC SRAM 18MBIT 167MHZ 165FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M(1M x 8,512K x 16) 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA(7x7) 包裝:托盤
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