參數(shù)資料
型號: IDT71P79204
廠商: Integrated Device Technology, Inc.
英文描述: 18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
中文描述: 35.7流水線⑩二二氧化硅的DDR SRAM的爆裂2
文件頁數(shù): 11/23頁
文件大?。?/td> 641K
代理商: IDT71P79204
6.42
11
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range
(V
DD
= 1.8 ± 100mV, V
DDQ
= 1.4V to 1.9V)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Note
Input Leakage Current
I
IL
V
DD
= Max V
IN
= V
SS
to V
DDQ
-2
+2
uA
Output Leakage Current
I
OL
Output Disabled
-2
+2
uA
Com'l
Ind
Operating Current
(x36): DDR
I
DD
V
DD
= Max,
I
OUT
= 0mA (outputs open),
Cycle Time > t
KHKH
Mn
250MH
Z
-
1050
1100
mA
1
200MHz
-
950
1000
167MHz
-
850
900
Operating Current
(x18): DDR
I
DD
V
DD
= Max,
I
OUT
= 0mA (outputs open),
Cycle Time > t
KHKH
Mn
267MHz
-
950
980
mA
1
250MH
Z
-
850
900
200MHz
-
750
800
167MHz
-
650
700
Operating Current
(x9,x8): DDR
I
DD
V
DD
= Max,
I
OUT
= 0mA (outputs open),
Cycle Time > t
KHKH
Mn
250MH
Z
-
800
850
mA
1
200MHz
-
700
750
167MHz
-
600
650
Standby Current: NOP
I
SB1
Device Deselected (in NOP state)
I
OUT
= 0mA (outputs open),
f=Max,
All Inputs <0.2V or > VDD -0.2V
267MHz
-
420
450
mA
2
250MH
Z
-
375
410
200MHz
-
335
370
167MHz
-
300
335
Output High Voltage
V
OH1
RQ = 250
,
I
OH
= -15mA
V
DDQ
/2-0.12
V
DDQ
/2+0.12
V
3,7
Output Low Voltage
V
OL1
RQ = 250
,
I
OL
= 15mA
V
DDQ
/2-0.12
V
DDQ
/2+0.12
V
4,7
Output High Voltage
V
OH2
I
OH
= -0.1mA
V
DDQ
-0.2
V
DDQ
V
5
Output Low Voltage
V
OL2
I
OL
= 0.1mA
V
SS
0.2
V
6
6432 tbl 10c
NOTES:
1. Operating Current is calculated with 50% read cycles and 50% write cycles.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175
< RQ < 350
.
This
parameter is tested at RQ = 250
,
which gives a nomnal 50
output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175
< RQ < 350
.
This
parameter is tested at RQ = 250
,
which gives a nomnal 50
output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an
impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.
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IDT71P79604 18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
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