參數(shù)資料
型號(hào): IDT71V124SA20YI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout
中文描述: 128K X 8 STANDARD SRAM, 20 ns, PDSO32
封裝: 0.400 INCH, PLASTIC, SOJ-32
文件頁數(shù): 4/8頁
文件大?。?/td> 81K
代理商: IDT71V124SA20YI
4
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
NOTES:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
Symbol
Parameter
71V124SA10
71V124SA12
71V124SA15
71V124SA20
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
10
____
12
____
15
____
20
____
ns
t
AA
Address Access Time
____
10
____
12
____
15
____
20
ns
t
ACS
Chip Select Access Time
____
10
____
12
____
15
____
20
ns
t
CLZ
(1)
Chip Select to Output in Low-Z
4
____
4
____
4
____
4
____
ns
t
CHZ
(1)
Chip Deselect to Output in High-Z
0
5
0
6
0
7
0
8
ns
t
OE
Output Enable to Output Valid
____
5
____
6
____
7
____
8
ns
t
OLZ
(1)
Output Enable to Output in Low-Z
0
____
0
____
0
____
0
____
ns
t
OHZ
(1)
Output Disable to Output in High-Z
0
5
0
5
0
5
0
7
ns
t
OH
Output Hold fromAddress Change
4
____
4
____
4
____
4
____
ns
WRITE CYCLE
t
WC
Write Cycle Time
10
____
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write
7
____
8
____
10
____
12
____
ns
t
CW
Chip Select to End-of-Write
7
____
8
____
10
____
12
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
7
____
8
____
10
____
12
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write
5
____
6
____
7
____
9
____
ns
t
DH
Data Hold Time
0
____
0
____
0
____
0
____
ns
t
OW
(2)
Output Active fromEnd-of-Write
3
____
3
____
3
____
4
____
ns
t
WHZ
(2)
Write Enable to Output in High-Z
0
5
0
5
0
5
0
8
ns
3873 tbl 08
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