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參數(shù)資料
| 型號： | IDT71V256SA15PZI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | LOW POWER 3.3V CMOS FAST SRAM 256K (32K x 8-BIT) |
| 中文描述： | 32K X 8 CACHE SRAM, 15 ns, PDSO28 |
| 封裝： | 0.300 INCH, TSOP1-28 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 67K |
| 代理商： | IDT71V256SA15PZI |
5
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 2, 4)
TIMING WAVEFORM OF READ CYCLE NO. 3
(1, 3, 4)
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
is LOW.
5. Transition is measured
±
200mV from steady state.
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3. t
WR
is measured from the earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured
±
200mV from steady state.
7. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+ t
DW
) to allow the I/O drivers to turn off and data
to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the write pulse can
be as short as the spectified t
WP.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED TIMING)
(1, 2, 3, 5, 7)
ADDRESS
DATA
OUT
3101 drw 07
t
RC
t
AA
t
OH
t
OH
DATA VALID
PREVIOUS DATA VALID
DATA
OUT
CS
3101 drw 08
t
ACS
(5)
t
CLZ
(5)
CHZ
t
DATA VALID
CS
DATA
IN
ADDRESS
WE
DATA
OUT
OE
3101 drw 09
t
AW
t
WR
t
DW
t
WC
t
WP
t
DH
t
WHZ
t
OW
(4)
(7)
t
AS
(6)
(4)
t
OHZ
(6)
DATA VALID
(6)
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相關代理商/技術(shù)參數(shù) |
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| IDT71V256SA15PZI8 | 功能描述:IC SRAM 256KBIT 15NS 28TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應商設備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
| IDT71V256SA15TP | 制造商:Integrated Device Technology Inc 功能描述:Static RAM, 32Kx8, 28 Pin, Plastic, DIP |
| IDT71V256SA15Y | 功能描述:IC SRAM 256KBIT 15NS 28SOJ RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應商設備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
| IDT71V256SA15Y8 | 功能描述:IC SRAM 256KBIT 15NS 28SOJ RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應商設備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
| IDT71V256SA15YG | 功能描述:IC SRAM 256KBIT 15NS 28SOJ RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-MSOP 包裝:帶卷 (TR) |
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