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    參數(shù)資料
    型號(hào): IDT71V321S25PFI
    廠商: INTEGRATED DEVICE TECHNOLOGY INC
    元件分類: DRAM
    英文描述: HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
    中文描述: 2K X 8 DUAL-PORT SRAM, 25 ns, PQFP64
    封裝: TQFP-64
    文件頁(yè)數(shù): 4/14頁(yè)
    文件大?。?/td> 129K
    代理商: IDT71V321S25PFI
    6.42
    IDT71V321/71V421S/L
    High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
    34%54%"
    "$"")*#
    !
    *
    + / *6/ *!
    NOTES:
    1. 'X' in part numbers indicates power rating (S or L).
    2. V
    CC
    = 3.3V, T
    A
    = +25
    °
    C, and are not production tested. I
    CCDC
    = 70mA (Typ.).
    3. At f = f
    MAX
    , address and control lines (except Output Enable) are cycling at the maximumfrequency read cycle of 1/t
    RC
    and using "AC Test Conditions" of input levels
    of GND to 3V.
    4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
    5. Port "A" may be either left or right port. Port "B" is opposite fromport "A".
    Symbol
    Parameter
    Test Condition
    Version
    71V321X25
    71V421X25
    Com'l
    & Ind
    71V321X35
    71V421X35
    Com'l Only
    71V321X55
    71V421X55
    Com'l Only
    Unit
    Typ.
    Max.
    Typ.
    Max.
    Typ.
    Max.
    I
    CC
    Dynamc Operating
    Current
    (Both Ports Active)
    CE
    = V
    IL
    , Outputs Disabled
    SEM
    = V
    IH
    f = f
    MAX
    (3)
    COML
    S
    L
    55
    55
    130
    100
    55
    55
    125
    95
    55
    55
    115
    85
    mA
    IND
    S
    L
    55
    55
    150
    130
    ___
    ___
    ___
    ___
    I
    SB1
    Standby Current
    (Both Ports - TTL
    Level Inputs)
    CE
    R
    =
    CE
    = V
    IH
    SEM
    R
    =
    SEM
    L
    = V
    IH
    f = f
    MAX
    (3)
    COML
    S
    L
    15
    15
    35
    20
    15
    15
    35
    20
    15
    15
    35
    20
    mA
    IND
    S
    L
    15
    15
    50
    35
    ___
    ___
    ___
    ___
    I
    SB2
    Standby Current
    (One Port - TTL
    Level Inputs)
    CE
    "A"
    = V
    IL
    and
    CE
    "B"
    = V
    IH
    (5)
    Active Port Outputs Disabled,
    f=f
    (3)
    SEM
    R
    =
    SEM
    L
    = V
    IH
    COML
    S
    L
    25
    25
    75
    55
    25
    25
    70
    50
    25
    25
    60
    40
    mA
    IND
    S
    L
    25
    25
    95
    75
    ___
    ___
    ___
    ___
    I
    SB3
    Full Standby Current
    (Both Ports - All
    CMOS Level Inputs)
    Both Ports
    CE
    L
    and
    CE
    R
    > V
    CC
    - 0.2V
    V
    IN
    > V
    CC
    - 0.2V or
    V
    < 0.2V, f = 0
    (4)
    SEM
    R
    =
    SEM
    L
    > V
    CC
    - 0.2V
    COML
    S
    L
    1.0
    0.2
    5
    3
    1.0
    0.2
    5
    3
    1.0
    0.2
    5
    3
    mA
    IND
    S
    L
    1.0
    0.2
    10
    6
    ___
    ___
    ___
    ___
    I
    SB4
    Full Standby Current
    (One Port - All
    CMOS Level Inputs)
    CE
    "A"
    < 0.2V and
    CE
    "B"
    > V
    - 0.2V
    (5)
    SEM
    R
    =
    SEM
    L
    > V
    CC
    - 0.2V
    V
    IN
    > V
    CC
    - 0.2V or V
    IN
    < 0.2V
    Active Port Outputs Disabled
    f = f
    MAX
    (3)
    COML
    S
    L
    25
    25
    70
    55
    25
    25
    65
    50
    25
    25
    55
    40
    mA
    IND
    S
    L
    25
    25
    85
    70
    ___
    ___
    ___
    ___
    3026 tbl 06
    #4
    Symbol
    7*%)!
    Parameter
    Test Condition
    Mn.
    Typ.
    (1)
    Max.
    Unit
    V
    DR
    V
    CC
    for Data Retention
    2.0
    ___
    0
    V
    I
    CCDR
    Data Retention Current
    V
    CC
    = 2
    V,
    CE
    > V
    CC
    - 0.2V
    COML.
    ___
    100
    1500
    μA
    t
    CDR
    (3)
    Chip Deselect to Data
    Retention Time
    V
    IN
    > V
    CC
    - 0.2V or V
    IN
    < 0.2V
    IND.
    ___
    100
    4000
    μA
    0
    ___
    ___
    V
    t
    R
    (3)
    Operation Recovery Time
    t
    RC
    (2)
    ___
    ___
    V
    3026 tbl 07
    NOTES:
    1. V
    CC
    = 2V, T
    A
    = +25
    °
    C, and is not production tested.
    2. t
    RC
    = Read Cycle Time.
    3. This parameter is guaranteed by device characterization but not production tested.
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