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參數(shù)資料
| 型號： | IDT71V321S25TFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT |
| 中文描述： | 2K X 8 DUAL-PORT SRAM, 25 ns, PQFP64 |
| 封裝： | STQFP-64 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 129K |
| 代理商： | IDT71V321S25TFI |
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
&@@@A$$
BUSY
&
&@/9
#$;8
:!
NOTES:
1. Pins
BUSY
L
and
BUSY
R
are both outputs for IDT71V321 (master). Both are inputs
for IDT71V421 (slave).
BUSY
X
outputs on the IDT71V321 are totem-pole. On
slaves the
BUSY
X
input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable
inputs of this port. 'H' if the inputs to the opposite port became stable after the
address and enable inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= LOW will result.
BUSY
L
and
BUSY
R
outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when
BUSY
L
outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when
BUSY
R
outputs are driving LOW regardless of actual logic level
on the pin.
4&
&@@/@"
:!
NOTES:
1. A
0L
–
A
10L
≠
A
0R
–
A
10R
.
2. If
BUSY
= L, data is not written.
3. If
BUSY
= L, data may not be valid, see t
WDD
and t
DDD
timng.
4. 'H' = V
IH
, 'L' = V
IL
, 'X' = DON
’
T CARE, 'Z' = High-impedance.
NOTES
:
1. Assumes
BUSY
L
=
BUSY
R
= V
IH
2. If
BUSY
L
= V
IL
, then No Change.
3. If
BUSY
R
= V
IL
, then No Change.
4. 'H' = HIGH, 'L' = LOW, 'X' = DON
’
T CARE
Left Port
Right Port
Function
R/
W
L
CE
L
OE
L
A
10L
-A
0L
INT
L
R/
W
R
CE
R
OE
R
A
10R
-A
0R
INT
R
L
L
X
7FF
X
X
X
X
X
L
(2)
Set Right
INT
R
Flag
X
X
X
X
X
X
L
L
7FF
H
(3)
Reset Right
INT
R
Flag
X
X
X
X
L
(3)
L
L
X
7FE
X
Set Left
INT
L
Flag
X
L
L
7FE
H
(2)
X
X
X
X
X
Reset Left
INT
L
Flag
3026 tbl 14
Inputs
Outputs
Function
CE
L
CE
R
A
OL
-A
10L
A
OR
-A
10R
BUSY
L
(1)
BUSY
R
(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit
(3)
3026 tbl 15
Left or Right Port
(1)
R/
W
CE
OE
D
0-7
Function
X
H
X
Z
Port Deselected and in Power-
Down Mode. I
SB2
or I
SB4
X
H
X
Z
CE
R
=
CE
L
= V
IH,
Power-Down Mode I
SB1
or I
SB3
L
L
X
DATA
IN
Data on Port WrittenInto Memory
(2)
H
L
L
DATA
OUT
Data in Memory Output on Port
(3)
H
L
H
Z
High-impedance Outputs
3026 tbl 13
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| IDT71V321S35J | 功能描述:IC SRAM 16KBIT 35NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT71V321S35J8 | 功能描述:IC SRAM 16KBIT 35NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT71V321S35PF | 功能描述:IC SRAM 16KBIT 35NS 64TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT71V321S35PF8 | 功能描述:IC SRAM 16KBIT 35NS 64TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT71V321S35TF | 功能描述:IC SRAM 16KBIT 35NS 64STQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
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