參數(shù)資料
型號(hào)： IDT71V3558SA166PFG
廠商： Integrated Device Technology, Inc.
英文描述： Ceramic Conformally Coated / Radial 'Standard & High Voltage Golden Max'; Capacitance [nom]: 75pF; Working Voltage (Vdc)[max]: 1000V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic, Conformally Coated; Temperature Coefficient: C0G (NP0); Lead Style: Radial Leaded; Lead Dimensions: 0.200" Lead Spacing; Body Dimensions: 0.300" x 0.390" x 0.200"; Container: Tape & Reel; Qty per Container: 1500
中文描述： 128K的× 36，256 × 18 3.3同步ZBT SRAM的3.3V的I / O的脈沖計(jì)數(shù)器輸出流水線
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 1010K
代理商： IDT71V3558SA166PFG
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Synchronous Truth Table
(1)
CEN
R/
W
Chip
(5)
Enable
USED
9
Partial Truth Table for Writes
(1)
NOTES:
1. L = V
IL
, H = V
IH
, X = Dont Care.
2. When ADV/
LD
signal is sampled high, the internal burst counter is incremented. The R/
W
signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determned by the status of the R/
W
signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (
CE
1
, or
CE
2
is sampled high or CE
2
is sampled low) and ADV/
LD
is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When
CEN
is sampled high at the rising edge of clock, that clock edge is blocked frompropogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires
CE
1
= L,
CE
2
= L, CE
2
= H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read fromthe device, D - data written to the device.
NOTES:
1. L = V
IL
, H = V
IH
, X = Dont Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
ADV/
LD
BW
x
ADDRESS
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(2 cycles later)
L
L
Select
L
Valid
External
X
LOAD WRITE
D
(7)
L
H
Select
L
X
External
X
LOAD READ
Q
(7)
L
X
X
H
Valid
Internal
LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)
(2)
D
(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
(Advance burst counter)
(2)
Q
(7)
L
X
Deselect
L
X
X
X
DESELECT or STOP
(3)
HiZ
L
X
X
H
X
X
DESELECT / NOOP
NOOP
HiZ
H
X
X
X
X
X
X
SUSPEND
(4)
Previous Value
5281 tbl 08
OPERATION
R/
W
BW
1
BW
2
BW
3
(3)
BW
4
(3)
READ
H
X
X
X
X
WRITE ALL BYTES
L
L
L
L
L
WRITE BYTE 1 (I/O[0:7], I/O
P1
)
(2)
L
L
H
H
H
WRITE BYTE 2 (I/O[8:15], I/O
P2
)
(2)
L
H
L
H
H
WRITE BYTE 3 (I/O[16:23], I/O
P3
)
(2,3)
L
H
H
L
H
WRITE BYTE 4 (I/O[24:31], I/O
P4
)
(2,3)
L
H
H
H
L
NO WRITE
L
H
H
H
H
5281 tbl 09
相關(guān)PDF資料
PDF描述
IDT71V3556S100BGG 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3556S100BGGI 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3556S100BQG 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3556S100BQGI 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3556S100PFGI 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs
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