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參數(shù)資料
| 型號(hào)： | IDT71V421L55PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT |
| 中文描述： | 2K X 8 DUAL-PORT SRAM, 55 ns, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁(yè)數(shù)： | 9/14頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | IDT71V421L55PF |
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6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
9
34%54
%""$"")*#
=!
NOTES:
1. Port-to-port delay through RAMcells fromthe writing port to the reading port, refer to
“
Timng Waveformof Write with Port-to-Port Read and
BUSY
."
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
–
t
WP
(actual) or t
DDD
–
t
DW
(actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
71V321X25
71V421X25
Com'l
& Ind
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
Symbol
Parameter
Mn.
Max.
Mn.
Max.
Mn.
Max.
Unit
BUSY
Timing (For Master IDT71V321 Only)
t
BAA
BUSY
Access Time fromAddress
____
20
____
20
____
30
ns
t
BDA
BUSY
Disable Time fromAddress
____
20
____
20
____
30
ns
t
BAC
BUSY
Access Time fromChip Enable
____
20
____
20
____
30
ns
t
BDC
BUSY
Disable Time fromChip Enable
____
20
____
20
____
30
ns
t
WH
Write Hold After
BUSY
(5)
12
____
15
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
50
____
60
____
80
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
35
____
45
____
65
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
30
____
30
____
45
ns
BUSY
Timing (For Slave IDT71V421 Only)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
12
____
15
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
50
____
60
____
80
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
35
____
45
____
65
ns
3026 tbl 11
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
"B"
DATA
OUT"B"
DATA
IN"A"
ADDR
"A"
MATCH
VALID
MATCH
VALID
R/
W
"A"
BUSY
"B"
t
APS
3026 drw 10
(1)
t
BAA
858>4#$$
BUSY
:!
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS
is ignored for SLAVE (71V421).
2.
CE
L
=
CE
R
= V
IL
3.
OE
= V
IL
for the reading port.
4. All timng is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite fromport "A".
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