參數(shù)資料
型號: IDT71V67902S85BQ
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
中文描述: 512K X 18 CACHE SRAM, 8.5 ns, PBGA165
封裝: 13 X 15 MM, FPBGA-165
文件頁數(shù): 1/23頁
文件大?。?/td> 527K
代理商: IDT71V67902S85BQ
DECEMBER 2003
DSC-5317/08
1
2002 Integrated Device Technology, Inc.
Pin Description Summary
A
0
-A
18
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS
0
,
CS
1
Chip Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW
1
,
BW
2
,
BW
3
,
BW
4
(1)
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
ZZ
Sleep Mode
Input
Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / Output
I/O
Synchronous
V
DD
, V
DDQ
Core Power I/O Power
Supply
N/A
V
SS
Ground
Supply
N/A
5317 tbl 01
Features
N
256K x 36, 512K x 18 memory configurations
N
Supports fast access times:
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
N
LBO
input selects interleaved or linear burst mode
N
Self-timed write cycle with global write control (
enable (
BWE
), and byte writes (
N
3.3V core power supply
N
Power down controlled by ZZ input
N
2.5V I/O supply (V
DDQ
)
N
Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA).
GW
), byte write
BW
x)
Description
The IDT71V67702/7902 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V67702/7902 SRAMs contain write,
NOTE:
1.
BW
3
and
BW
4
are not applicable for the IDT71V67902.
256K X 36, 512K X 18
3.3V Synchronous SRAMs
2.5V I/O, Burst Counter
Flow-Through Outputs, Single Cycle Deselect
IDT71V67702
IDT71V67902
data, address and control registers. There are no registers in the data
output path (flow-through architecture). Internal logic allows the SRAMto
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
systemdesigner, as the IDT71V67702/7902 can provide four cycles of
data for a single address presented to the SRAM An internal burst address
counter accepts the first cycle address fromthe processor, initiating the
access sequence. The first cycle of output data will flow-through fromthe
array after a clock-to-data access time delay fromthe rising clock edge of
the same cycle. If burst mode operation is selected (
ADV
=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the
LBO
input pin.
The IDT71V67702/7902 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mmx 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
相關PDF資料
PDF描述
IDT71V67902S85BQI 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
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