參數資料
型號: IDT72104L50J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
中文描述: 4K X 9 OTHER FIFO, 50 ns, PQCC44
封裝: PLASTIC, LCC-44
文件頁數: 11/31頁
文件大小: 314K
代理商: IDT72104L50J
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
5.37
11
R
(1)
EF
W
t
REF(2)
(3)
t
WEF
2753 drw 09
NOTES:
1. Data is valid on this edge.
2. The Empty Flag is asserted by
R
in the Parallel-Out mode and is specified by t
REF
. The
EF
flag is deasserted by the rising edge of
W
.
3. First rising edge of Write after
EF
is set.
Figure 6. Empty Flag Timings in Parallel Out Mode
R
FF
W
t
RFF(1)
t
WFF
2753 drw 10
NOTE:
1. For the assertion time, t
WFF
is used when data is written in the Parallel mode. The
FF
is de-asserted by the rising edge of
R
.
Figure 7. Full Flag Timings in Parallel-In Mode
R
AEF
W
t
WF
2753 drw 11
t
RF
Almost
Empty
Almost
Empty
R
AEF
W
t
WF
2753 drw 12
t
RF
Almost
Full
Figure 8. Almost-Empty Flag Region
Figure 9. Almost-Full Flag Region
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