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參數(shù)資料
| 型號： | IDT72104L50J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 |
| 中文描述： | 4K X 9 OTHER FIFO, 50 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 17/31頁 |
| 文件大?。?/td> | 314K |
| 代理商： | IDT72104L50J |
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IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
5.37
17
2753 drw 26
SICP
NEXT TO LAST
SERIAL WORD
1
LAST SERIAL
WORD
1
0
t
SICF
R
FF-1
W=D
n-1
t
SICFF
n-2
n-1
0
n-2
n-1
0
1
t
RFFSI
(1)
(2)
t
RFF
FF
2753 drw 27
SOCP
t
SOCFF
FIRST
SERIAL-OUT WORD
SECOND
SERIAL-OUT WORD
0
1
n – 1
0
1
n – 1
t
PD2
W
FF
FF-1
Q
n+1
=
R
(2)
t
SOCF
t
WFF
t
WF
(1)
NOTES:
1. The Full Flag is asserted in the Serial-ln mode by using the t
SICFF
parameter. This parameter is measured in the worst case condition from the rising
edge of SICP following a (t
PD1
+t
WFF
) delay from the first SICP rising edge of the last word.
2. First Read rising edge after
FF
is set.
3. After
FF
goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until
FF
goes HIGH.
Figure 23. Full Flag and Full-1 Flag Assertlon in the Serial-ln Mode (FIFO Being Filled)
NOTES:
1. The FIFO is full and a new read sequence is started.
2. On the first rising edge of SOCP, the
FF
is de-asserted. In the Serial-ln mode, a new write operation can begin following t
RFFS1
after
FF
, goes HIGH.
In the Parallel-ln mode, a new write operation can occur immediately after
FF
goes HIGH.
3. The
FF-1
flag is de-asserted after the first SOCP of the second serial word.
Figure 24. Full Flag and Full-1 Flag De-assertion in the Serial-Out Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72105 | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72105L25SO | Current-Mode PWM Controller 14-SOIC -40 to 85 |
| IDT72105L25TP | Current-Mode PWM Controller 8-SOIC -40 to 85 |
| IDT72115L25SO | TRANS PNP HF 40VCEO 1.5A TO-126 |
| IDT72115L25TP | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72104S120P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72104S50D | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:4K X 9 OTHER FIFO, 50 ns, CDIP40 |
| IDT72104S50P | 制造商:IDT/89'S 功能描述:FIFO, 4K x 9, Asynchronous, 40 Pin, Plastic, DIP |
| IDT72105L50S0 | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72105L50TP | 制造商:INT_DEV_TECH 功能描述: |
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