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參數(shù)資料
| 型號(hào)： | IDT72105L50SO |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| 中文描述： | 256 X 16 OTHER FIFO, 50 ns, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 179K |
| 代理商： | IDT72105L50SO |
5.35
5
COMMERCIAL TEMPERATURE RANGE
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
2665 tbl 07
NOTES:
1.
EF
,
FF
,
HF
and
AEF
may change status during Reset, but flags will be valid at t
RSC.
2. SOCP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR.
Figure 1. Reset
FUNCTIONAL DESCRIPTION
Parallel Data Input
The device must be reset before beginning operation so
that all flags are set to their initial state. In width or depth
expansion the First Load pin (
FL
) must be programmed to
indicate the first device.
The data is written into the FIFO in parallel through the D
0–
15
input data lines. A write cycle is initiated on the falling edge
of the Write (
W
) signal provided the Full Flag (
FF
) is not
asserted. If the
W
signal changes from HIGH-to-LOW and the
Full Flag (
FF
) is already set, the write line is internally inhibited
internally from incrementing the write pointer and no write
operation occurs.
Data set-up and hold times must be met with respect to the
rising edge of Write. On the rising edge of
W
, the write pointer
is incremented. Write operations can occur simultaneously or
asynchronously with read operations.
Serial Data Output
The serial data is output on the SO pin. The data is clocked
out on the rising edge of SOCP providing the Empty Flag (
EF
)
is not asserted. If the Empty Flag is asserted then the next data
word is inhibited from moving to the output register and being
clocked out by SOCP.
The serial word is shifted out Least Significant Bit or Most
Significant Bit first, depending on the
FL
/DIR level during
operation. A LOW on DIR will cause the Least Significant Bit
to be read out first. A HIGH on DIR will cause the Most
Significant Bit to be read out first.
CAPACITANCE
(T
A
= +25
°
C, f = 1.0MHz)
Parameter
(1)
C
IN
Input Capacitance
C
OUT
Output
Capacitance
NOTE:
1. This parameter is sampled and not 100% tested.
Symbol
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
12
Unit
pF
pF
2665 tbl 08
W
t
RSC
RS
AEF, EF
HF, FF
FLAG
STABLE
FLAG
STABLE
2665 drw 04
t
RSC
t
RSS
t
RSR
t
RSC
t
RS
SOCP
t
RSS
t
RSR
NOTE 2
t
FLS
t
FLH
FL/DIR
GND to 3.0V
5ns
1.5V
1.5V
See Figure A
or equivalent circuit
Figure A. Output Load
*Includes jig and scope capacitances.
2665 drw 03
1.1K
30pF
680
5V
TO
OUTPUT
PIN
*
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72115L50SO | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72125L50SO | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72105L50TP | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72115L50TP | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72125L50TP | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
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|---|---|
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