參數(shù)資料
型號(hào): IDT72142
廠商: Integrated Device Technology, Inc.
英文描述: CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 4096 x 9
中文描述: CMOS串行到并行FIFO的2048 × 9 4096 × 9
文件頁數(shù): 10/13頁
文件大小: 137K
代理商: IDT72142
5.36
10
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
Single Device Configuration
In the standalone case, the SIX line is tied HIGH and not
used. On the first LOW-to-HIGH of the SICP clock, both of the
Data Set lines (D
7
, D
8
) go LOW and a new serial word is
started. The Data Set lines then go HIGH on the equivalent
SICP clock pulse. This continues until the D line connected to
NW
goes HIGH completing the serial word. The cycle is then
repeated with the next LOW-to-HIGH transition of SICP.
TRUTH TABLES
TABLE 1: RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs
FL
/
RT
X
0
1
Internal Status
Outputs
FF
1
X
X
Mode
RS
0
1
1
XI
0
0
0
Read Pointer
Location Zero
Location Zero
Increment
(1)
Write Pointer
Location Zero
Unchanged
Increment
(1)
AEF
,
EF
0
X
X
HF
1
X
X
Reset
Retransmit
Read/Write
NOTE:
1. Pointer will increment if appropriate flag is HIGH.
2752 tbl 09
2752 drw 16
SICP
NW
V
CC
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
D
7
D
8
SICP
SIX
SERIAL INPUT CLOCK
SI
XI
PARALLEL DATA OUTPUT
GND
SERIAL DATA IN
Q
0-8
NW
D
7
D
8
8
0
Figure 13. Nine-Bit Word Single Device Configuration
相關(guān)PDF資料
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