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參數(shù)資料
| 型號(hào)： | IDT72142 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 4096 x 9 |
| 中文描述： | CMOS串行到并行FIFO的2048 × 9 4096 × 9 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 137K |
| 代理商： | IDT72142 |
5.36
5
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure A
2752 tbl 08
Figure 1. Reset
NOTE:
1. Input bits are numbered 0 to n-1. D
7
and D
8
correspond to n=8 and n=9 respectively
FUNCTIONAL DESCRIPTION
Serial Data Input
The serial data is input on the SI pin. The data is clocked
in on the rising edge of SICP providing the Full Flag (
FF
) is not
asserted. If the Full Flag is asserted then the next parallel data
word is inhibited from moving into the RAM array. NOTE:
SICP should not be clocked once the last bit of the last word
has been shifted in, as indicated by
NW
HIGH and
FF
LOW.
If it is, then the input data will be lost.
The serial word is shifted in Least Significant Bit first. Thus,
when the FIFO is read, the Least Significant Bit will come out
on Q
0
and the second bit is on Q
1
and so on. The serial word
width must be programmed by connecting the appropriate
Data Set line (D
7
, D
8
) to the
NW
input. The data set lines are
taps off a digital delay line. Selecting one of these taps
programs the width of the serial word to be written in.
*Includies jig and scope capacitances
Figure A. Output Load
or equivalent circuit
1.1K
30pF*
680
5V
D.U.T.
2752 drw 03
2752 drw 04
R
RS
AEF
,
EF
HF
,
FF
t
RSC
t
RS
t
RSS
t
RSR
t
RSS
t
RSF1
t
RSF2
t
RSDL
t
PDI
SICP
D ,D
7
8
0
n-1
(1)
Parallel Data Output
A read cycle is initiated on the falling edge of Read (
R
)
provided the Empty Flag is not set. The output data is
accessed on a first-in/first-out basis, independent of the
ongoing write operations. The data is available t
A
after the
falling edge of
R
and the output bus Q goes into high imped-
ance after
R
goes HIGH.
Alternately, the user can access the FIFO by keeping
R
LOW and enabling data on the bus by asserting Output Enable
(
OE
). When
R
is LOW, the
OE
signal enables data on the
output bus. When
R
is LOW and
OE
is HIGH, the output bus
is three-stated. When
R
is HIGH, the output bus is disabled
irrespective of
OE
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72142L35P | CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 4096 x 9 |
| IDT72132L50P | Silver Mica Capacitor; Capacitance:910pF; Capacitance Tolerance:+/- 5%; Series:CDS; Voltage Rating:100VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.9mm; Leaded Process Compatible:No RoHS Compliant: No |
| IDT72142L50P | Silver Mica Capacitor; Capacitance:100pF; Capacitance Tolerance:+/- 5%; Series:CDV16; Voltage Rating:1000VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.94mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| IDT7216L55C | 16 x 16 PARALLEL CMOS MULTIPLIERS |
| IDT7217L55JB | 16 x 16 PARALLEL CMOS MULTIPLIERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72156 | 制造商:IDT 功能描述:72156 |
| IDT7216L25FB | 制造商:Integrated Device Technology Inc 功能描述:MULTIPLIER, 64 Pin, Ceramic, Quad CERPAK |
| IDT7216L55GB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT7217L25J | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72200L10TP | 功能描述:IC FIFO 200KB SYNC 10NS 28DIP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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