參數(shù)資料
型號(hào): IDT72255LA20PFI8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 1/27頁(yè)
文件大?。?/td> 0K
描述: IC FIFO 8KX18 LP 20NS 64QFP
標(biāo)準(zhǔn)包裝: 750
系列: 7200
功能: 同步
存儲(chǔ)容量: 144K(8K x 18)
訪問(wèn)時(shí)間: 20ns
電源電壓: 4 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72255LA20PFI8
1
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4670/3
JANUARY 2009
CMOS SuperSync FIFO
8,192 x 18
16,384 x 18
IDT72255LA
IDT72265LA
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync FIFO is a trademark of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES
Choose among the following memory organizations:
IDT72255LA
8,192 x 18
IDT72265LA
16,384 x 18
Pin-compatible with the IDT72275/72285 SuperSync FIFOs
10ns read/write cycle time (8ns access time)
Fixed, low first word data latency time
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Retransmit operation with fixed, low first word data latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using
OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and writing
simultaneously)
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
DESCRIPTION
The IDT72255LA/72265LA are exceptionally deep, high speed, CMOS
First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrols. These
FIFOs offer numerous improvements over previous SuperSync FIFOs,
including the following:
Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
The period required by the retransmit operation is now fixed and short.
Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
8,192 x 18
16,384 x 18
FLAG
LOGIC
FF /IR
PAF
EF /OR
PAE
HF
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN
WCLK
D0 -D17
LD
MRS
REN
RCLK
OE
Q0 -Q17
OFFSET REGISTER
PRS
FWFT/SI
SEN
RT
4670 drw01
FUNCTIONAL BLOCK DIAGRAM
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