參數(shù)資料
型號(hào): IDT72255LA20PFI8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 24/27頁(yè)
文件大小: 0K
描述: IC FIFO 8KX18 LP 20NS 64QFP
標(biāo)準(zhǔn)包裝: 750
系列: 7200
功能: 同步
存儲(chǔ)容量: 144K(8K x 18)
訪問(wèn)時(shí)間: 20ns
電源電壓: 4 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72255LA20PFI8
6
IDT72255LA/72265LA CMOS SuperSync FIFO
8,192 x 18 and 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 13, 2009
4670 drw04
1.1K
30pF*
680
5V
D.U.T.
* Includes jig and scope capacitances.
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figure 2
AC TEST CONDITIONS
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
Figure 2. Output Load
Commercial
Commercial & Industrial(2)
IDT72255LA10
IDT72255LA15
IDT72255LA20
IDT72265LA10
IDT72265LA15
IDT72265LA20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
100
66.7
50
MHz
tA
Data Access Time
2
8
2
10
2
12
ns
tCLK
Clock Cycle Time
10
15
20
ns
tCLKH
Clock High Time
4.5
6
8
ns
tCLKL
Clock Low Time
4.5
6
8
ns
tDS
DataSetupTime
3
4
5
ns
tDH
Data Hold Time
0
1
1
ns
tENS
Enable Setup Time
3
4
5
ns
tENH
Enable Hold Time
0
1
1
ns
tLDS
LoadSetupTime
3
4
5
ns
tLDH
Load Hold Time
0
1
1
ns
tRS
Reset Pulse Width(3)
10
15
20
ns
tRSS
ResetSetupTime
10
15
20
ns
tRSR
Reset Recovery Time
10
15
20
ns
tRSF
Reset to Flag and Output Time
10
15
20
ns
tFWFT
Mode Select Time
0
0
0
ns
tRTS
RetransmitSetupTime
3
4
5
ns
tOLZ
Output Enable to Output in Low Z(4)
0
0—
ns
tOE
Output Enable to Output Valid
2
6
3
8
3
10
ns
tOHZ
Output Enable to Output in High Z(4)
2
638
3
10
ns
tWFF
Write Clock to
FF or IR
—8
10
12
ns
tREF
Read Clock to
EF or OR
—8
10
12
ns
tPAF
Write Clock to
PAF
—8
10
12
ns
tPAE
Read Clock to
PAE
—8
10
12
ns
tHF
Clock to
HF
—16
20
22
ns
tSKEW1
Skew time between RCLK and WCLK for
FF/IR
5—
6
10
ns
tSKEW2
Skew time between RCLK and WCLK for
PAE and PAF
12
15
20
ns
tSKEW3
Skew time between RCLK and WCLK for
EF/OR
60
60
60
ns
tSKEW4
Skew time between RCLK and WCLK for
PAE and PAF
15
17
25
ns
forRe-transmitoperation
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0
°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
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