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參數(shù)資料
| 型號(hào)： | IDT72261L12TF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
| 中文描述： | 16K X 9 OTHER FIFO, 9 ns, PQFP64 |
| 封裝： | STQFP-64 |
| 文件頁(yè)數(shù)： | 9/30頁(yè) |
| 文件大?。?/td> | 388K |
| 代理商： | IDT72261L12TF |
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9
IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SERIAL ENABLE (
Serial Enable is
(
SEN
) is an enable used only for serial
programming of the offset registers. The serial programming
method must be selected during Master Reset.
SEN
is always
used in conjunction with
LD
. When these lines are both LOW,
data at the SI input can be loaded into the input register one
bit for each LOW-to-HIGH transition of WCLK.
When
SEN
is HIGH, the programmable registers retains
the previous settings and no offsets are loaded.
SEN
functions the same way in both IDT Standard and
FWFT modes.
SEN
)
OUTPUT ENABLE (
When Output Enable (
OE
) is enabled (LOW), the parallel
output buffers receive data from the output register. When
OE
is HIGH, the output data bus (Q
n
) goes into a high impedance
state.
OE
)
LOAD (
This is a dual purpose pin. During Master Reset, the state
of the Load line (
LD
) determines one of two default values (127
or 1023) for the
PAE
and
PAF
flags, along with the method by
which these flags can be programmed, parallel or serial. After
LD
)
Master Reset,
LD
enables write operations to and read
operations from the registers. Only the offset loading method
currently selected can be used to write to the registers. Aside
from Master Reset, there is no other way change the loading
method. Registers can be read only in parallel; this can be
accomplished regardless of whether serial or the parallel
loading has been selected.
Associated with each of the programmable flags,
PAE
and
PAF
, are two registers which can either be written to or read
from. Offset values contained in these registers determine
how many words need to be in the FIFO memory to switch a
partial flag. A LOW on
LD
during Master Reset selects a
default
PAE
offset value of 07FH ( a threshold 127 words from
the empty boundary), a default
PAF
offset value of 07FH (a
threshold 127 words from the full boundary), and parallel
loading of other offset values. A HIGH on
LD
during Master
Reset selects a default
PAE
offset value of 3FFH (a threshold
1023 words from the empty boundary), a default
PAF
offset
value of 3FFH (a threshold 1023 words form the full bound-
ary), and serial loading of other offset values.
The act of writing offsets (in parallel or serial) employs a
dedicated write offset register pointer. The act of reading
offsets employs a dedicated read offset register pointer. The
Figure 2. Partial Flag Programming Sequence
NOTES:
1. Only one of the two offset programming methods, serial or parallel, is available for use at any given time.
2. The programming method can only be selected at Master Reset.
3. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
4. The programming sequence applies to both IDT Standard and FWFT modes.
WCLK
RCLK
Selection
X
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
X
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
X
X
No Operation
X
Write Memory
X
Read Memory
X
X
No Operation
3097 tbl 01
LD
0
0
X
1
1
1
0
WEN
0
1
1
0
X
1
1
REN
1
0
1
X
0
1
1
X
Serial shift into registers:
28 bits for the 72261
30 bits for the 72271
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
SEN
1
1
1
X
X
X
0
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| IDT72261L15GB | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
| IDT72261L15PF | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
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| IDT72261L15TF | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
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| IDT72261LA10PF | 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA10PF8 | 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA10TF | 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA10TF8 | 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA15PF | 功能描述:IC FIFO 8192X18 LP 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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