參數(shù)資料
型號(hào): IDT72265L20PFB
廠商: Integrated Device Technology, Inc.
英文描述: Bi-Directional Triode Thyristor Planar Silicon
中文描述: 的CMOS SUPERSYNC FIFOO 8192 × 18,16,384 × 18
文件頁(yè)數(shù): 22/30頁(yè)
文件大?。?/td> 394K
代理商: IDT72265L20PFB
22
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72255/72265 SyncFIFO
8,192 x 18, 16,384 x 18
NOTES:
1.
PAE
offset = n
2. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
to the output register (no read operation necessary), it is not included in the FIFO memory count.
3. t
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge for
PAE
to go HIGH (after one RCLK cycle plus t
PAE
). If the time
between the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
, then the
PAE
deassertion may be delayed one extra RCLK cycle.
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAE
RCLK
REN
3037 drw 17
t
ENS
t
ENH
t
ENS
n words in FIFO memory
t
PAE
n+1 words in FIFO memory
t
SKEW2
t
PAE
1
2
1
2
n Words
in FIFO
memory
(1,2)
(3)
Figure 13. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT modes)
NOTE:
1.
OE
=LOW
Figure 14. Programmable Almost Empty Flag Timing (IDT Standard and FWFT modes)
RCLK
LD
REN
Q0 - Q17
t
LDH
t
LDS
t
CLKH
t
CLKL
t
ENS
DATA IN OUTPUT REGISTER
PAE OFFSET
PAF OFFSET
t
ENH
t
ENH
t
ENH
3037 drw 16
t
CLK
t
A
t
A
相關(guān)PDF資料
PDF描述
IDT72265L20TF Bi-Directional Triode Thyristor Planar Silicon; Package: TO-220F; No of Pins: 3; Container: Rail
IDT72265L20TFB Bi-Directional Triode Thyristor Planar Silicon
IDT72265L25G Bi-Directional Triode Thyristor Planar Silicon; Package: TO-220F; No of Pins: 3; Container: Rail
IDT72265L25GB Bi-Directional Triode Thyristor Planar Silicon
IDT72265L25PF Bi-Directional Triode Thyristor Planar Silicon; Package: TO-220F; No of Pins: 3; Container: Rail
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