參數(shù)資料
型號: IDT72265L20PFB
廠商: Integrated Device Technology, Inc.
英文描述: Bi-Directional Triode Thyristor Planar Silicon
中文描述: 的CMOS SUPERSYNC FIFOO 8192 × 18,16,384 × 18
文件頁數(shù): 24/30頁
文件大?。?/td> 394K
代理商: IDT72265L20PFB
24
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72255/72265 SyncFIFO
8,192 x 18, 16,384 x 18
t
REF
t
RTS
t
ENH
W
x
t
DH
t
RTS
W
[y+1]
t
ENS
t
ENH
t
RTF1
3037 drw 20
t
A
t
ENS
(1,2)
t
ENS
W
y
WCLK
WEN
RCLK
REN
D
0
- D
17
RT
EF
PAF
HF
PAE
FF
Q
0
- Q
17
t
ENH
W
[x + 1]
t
SKEW2
1
2
3
2
1
t
ENS
t
DS
W
1
t
PAF
t
HF
t
PAE
t
A
t
ENH
t
ENS
t
DS
t
DH
t
ENH
t
REF
(3)
(4)
NOTES:
1. t
RTF1
contributes a variable delay to the overall retransmit recovery time:
t
RFTF1
max = 14*T
f
+ 3*T
RCLK
(in ns)
Where T
f
is either the RCLK or the WCLK period, whichever is shorter, and T
RCLK
is the RCLK period.
2. Retransmit set up is complete after
EF
returns HIGH, only then can a read operation begin. Write operations are permitted after one of two conditions
have been met:
EF
is HIGH or 14 cycles of the faster clock (RCLK or WCLK) have elapsed since the RCLK rising edge enabled by the
RT
pulse.
3. Following Retransmit Setup, the rising edge of RCLK that accesses the first memory location also initiates the updating of
HF
,
PAE
, and
PAF
.
4. No more than D-2 words (D = 8,192 words for the 72255, 16,384 words for the 72265) should have been written to the FIFO between Reset (Master or
Partial) and Retransmit Setup. Therefore,
FF
will be HIGH throughout the Restransmit Setup procedure.
5.
OE
=LOW
Figure 17. Retransmit Timing (IDT Standard mode)
相關(guān)PDF資料
PDF描述
IDT72265L20TF Bi-Directional Triode Thyristor Planar Silicon; Package: TO-220F; No of Pins: 3; Container: Rail
IDT72265L20TFB Bi-Directional Triode Thyristor Planar Silicon
IDT72265L25G Bi-Directional Triode Thyristor Planar Silicon; Package: TO-220F; No of Pins: 3; Container: Rail
IDT72265L25GB Bi-Directional Triode Thyristor Planar Silicon
IDT72265L25PF Bi-Directional Triode Thyristor Planar Silicon; Package: TO-220F; No of Pins: 3; Container: Rail
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