參數(shù)資料
型號(hào): IDT723616L20PF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 25/26頁(yè)
文件大?。?/td> 0K
描述: IC FIFO TRPL BUS 64X36X2 128QFP
標(biāo)準(zhǔn)包裝: 72
系列: 7200
功能: 同步
存儲(chǔ)容量: 4.6K(64 x 36 x2)
數(shù)據(jù)速率: 50MHz
訪問(wèn)時(shí)間: 20ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
其它名稱: 723616L20PF
8
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
Commercial
Com’l & Ind’l(1)
IDT723616L15
IDT723616L20
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Frequency, CLKA, CLKB, or CLKC
66.7
50
MHz
tCLK
Clock Cycle Time, CLKA, CLKB, or CLKC
15
20
ns
tCLKH
Pulse Duration, CLKA, CLKB, and CLKC
6
8
ns
tCLKL
Pulse Duration, CLKA, CLKB, and CLKC
6
8
ns
tDS
Setup Time, A0-A35 before CLKA
↑ and C0-C17 before CLKC↑
4
–5–
ns
tENS
Setup Time,
CSA, W/RA, and ENA before CLKA
↑; RENB before CLKB↑;
5
–5–
ns
WENC before CLKC
tSZS
Setup Time, SIZ0 and SIZ1 before CLKB
↑ and CLKC↑
4
–5–
ns
tSWS
Setup Time, SWB0 and SWB1 before CLKB
↑,SWCOandSWC1,beforeCLKC↑
5
–7–
ns
tPGS
Setup Time, ODD/
EVEN and PGA before CLKA
↑; ODD/EVEN and PGB before
4
5
ns
CLKB
(2)
tRSTS
Setup Time,
RST LOW before CLKA
↑, CLKB↑, or CLKC↑(3)
5
–6–
ns
tFSS
Setup Time, FS0 and FS1 before
RST HIGH
5
6
ns
tDH
Hold Time, A0-A35 after CLKA
↑ and C0-C17 after CLKC↑
1
–1–
ns
tENH
Hold Time,
CSA, W/RA, and ENA after CLKA
↑; RENB after CLKB↑;WENB
1
1
ns
after CLKC
tSZH
Hold Time, SIZ0 and SIZ1 after CLKB
↑ and CLKC↑
2
–2–
ns
tSWH
Hold Time, SWB0 and SWB1 after CLKB
↑,SWC0andSWC1afterCLKC↑
0
–0–
ns
tPGH
Hold Time, ODD/
EVEN and PGA after CLKA
↑; ODD/EVEN and PGB after
0
0
ns
CLKB
(2)
tRSTH
Hold Time,
RST LOW after CLKA
↑, CLKB↑ or CLKC↑(2)
5
–6–
ns
tFSH
Hold Time, FS0 and FS1 after
RST HIGH
4
4
ns
tSKEW1(4)
Skew Time, between CLKA
↑ and CLKB↑ for EFB and FFA; between CLKC↑
8
–8–
ns
and CLKA
↑ for EFA and FFC
tSKEW2(4)
Skew Time, between CLKA
↑ and CLKB↑ for AEB and AFA; between CLKC↑
14
16
ns
and CLKA
↑ for AEA and AFC
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Only applies for a clock edge that does a FIFO read.
3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationships among CLKA cycle, CLKB cycle and CLKC.
(Commercial: VCC = 5.0V ±10%, TA = 0
°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
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