參數(shù)資料
型號： IDT723616L20PF
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 3/26頁
文件大?。?/td> 0K
描述： IC FIFO TRPL BUS 64X36X2 128QFP
標(biāo)準(zhǔn)包裝： 72
系列： 7200
功能： 同步
存儲容量： 4.6K（64 x 36 x2）
數(shù)據(jù)速率： 50MHz
訪問時間： 20ns
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
其它名稱： 723616L20PF
11
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
SYNCHRONIZED FIFO FLAGS
EachFIFOissynchronizedtoitsPortClockthroughtwoflip-flopstages.This
is done to improve flag reliability by reducing the probability of metastable
events on the output when CLKA operates asynchronously relative to CLKB
or CLKC.
EFA,AEA,FFA,andAFAaresynchronizedtoCLKA.EFBandAEB
are synchronized to CLKB.
FFCandAFCaresynchronizedtoCLKC.Tables
5 and 6 show the relationship of each port flag to FIFO1 and FIFO2.
EMPTY FLAGS (
EFA, EFB)
The empty flag of a FIFO is synchronized to the Port Clock that reads
data from its array. When the empty flag is HIGH, new data can be read
to the FIFO output register. When the empty flag is LOW, the FIFO is
empty and attempted FIFO reads are ignored. When reading FIFO1 with
a byte or word size on Port B,
EFB is set LOW when the fourth byte or
second word of the last long word is read.
The read pointer of a FIFO is incremented each time a new word is
clocked to the output register. The state machine that controls an empty
flag monitors a write-pointer and read-pointer comparator that indicates when
theFIFOSRAMstatusisempty,empty+1,orempty+2.AwordwrittentoaFIFO
canbereadtotheFIFOoutputregisterinaminimumofthreecyclesoftheempty
flag synchronizing clock. Therefore, an empty flag is LOW if a word in memory
is the next data to be sent to the FIFO output register and two cycles of the Port
Clock that reads data from the FIFO have not elapsed since the time the word
was written. The empty flag of the FIFO is set HIGH by the second LOW-to-
HIGHtransitionofthesynchronizingclock,andthenewdatawordcanberead
to the FIFO output register in the following cycle.
A LOW-to-HIGH transition on an empty flag synchronizing clock begins the
firstsynchronizationcycleofawriteiftheclocktransitionoccursattimetSKEW1
or greater after the write. Otherwise, the subsequent clock cycle can be the
first synchronization cycle (see Figure 12 and 13).
FULL FLAG (
FFA, FFC)
The full flag of a FIFO is synchronized to the Port Clock that writes data to
its array. When the full flag is HIGH, a memory location is free in the SRAM
to receive new data. No memory locations are free when the full flag is LOW
and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is incremented.
The state machine that controls a full flag monitors a write-pointer and
read-pointercomparatorthatindicateswhentheFIFOSRAMstatusisfull,full-
1, or full-2. From the time a word is read from a FIFO, the previous memory
location is ready to be written in a minimum of three cycles of the full flag
synchronizing clock. Therefore, a full flag is LOW if less than two cycles of the
fullflagsynchronizingclockhaveelapsedsincethenextmemorywritelocation
has been read. The second LOW-to-HIGH transition on the full flag synchro-
nization clock after the read sets the full flag HIGH and the data can be written
in the following clock cycle.
A LOW-to-HIGH transition on a full flag synchronizing clock begins the first
synchronization cycle of a read if the clock transition occurs at time tSKEW1 or
greater after the read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle (see Figure 14 and 15).
ALMOST-EMPTY FLAGS (
AEA, AEB)
TheAlmost-EmptyflagofaFIFOissynchronizedtothePortClockthatreads
data from its array. The state machine that controls an Almost-Empty flag
monitors a write-pointer and a read-pointer comparator that indicates when
theFIFOSRAMstatusisalmost-empty,almost-empty+1,oralmost-empty+2.
The almost-empty state is defined by the value of the Almost-Full and Almost-
Empty Offset register (X). This register is loaded with one of four preset values
during a device reset (see Reset above). An Almost-Empty flag is LOW when
the FIFO contains X or less long words in memory and is HIGH when the FIFO
contains (X+1) or more long words.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
arerequiredafteraFIFOwritefortheAlmost-Emptyflagtoreflectthenewlevel
of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1) or more
long words remains LOW if two cycles of the synchronizing clock have not
elapsed since the write that filled the memory to the (X+1) level. An Almost-
Empty flag is set HIGH by the second LOW-to-HIGH transition of the
synchronizing clock after the FIFO write that fills memory to the (X+1) level.
ALOW-to-HIGHtransitionofanAlmost-Emptyflagsynchronizingclockbegins
the first synchronization cycle if it occurs at time tSKEW2 or greater after the
write that fills the FIFO to (X+1) long words. Otherwise, the subsequent
synchronizing clock cycle can be the first synchronization cycle (see Figure
16 and 17).
ALMOST-FULL FLAGS (
AFA, AFC)
The Almost-Full flag of a FIFO is synchronized to the Port Clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors
a write-pointer and read-pointer comparator that indicates when the FIFO
SRAMstatusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstate
isdefinedbythevalueoftheAlmost-FullandAlmost-EmptyOffsetregister(X).
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register.
TABLE 5 — FIFO1 FLAG OPERATION
TABLE 6 — FIFO2 FLAG OPERATION
Synchronized
Number of 36-Bit
to CLKA
to CLKC
Words in the FIFO2(1
EFA
AEA
AFC
FFC
0L
L
H
1 to X
H
L
H
(X+1) to [64–(X+1)]
H
(64–X)to 63
H
L
H
64
H
L
Synchronized
Number of 36-Bit
to CLKB
to CLKA
Words in the FIFO1(1)
EFB
AEB
AFA
FFA
0L
L
H
1 to X
H
L
H
(X+1) to [64–(X+1)]
H
(64–X) to 63
H
L
H
64
H
L
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