Figure 1. Output Load AC TEST CONDITIONS Input Pulse L" />
參數(shù)資料
型號: IDT72413L25SOG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 5/10頁
文件大?。?/td> 0K
描述: IC FIFO PAR W/FLAGS 32KB 20SOIC
標(biāo)準(zhǔn)包裝: 1,000
系列: 7200
功能: 異步
存儲容量: 32K
數(shù)據(jù)速率: 25MHz
訪問時間: 25ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 帶卷 (TR)
其它名稱: 72413L25SOG8
4
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5
COMMERCIALTEMPERATURERANGE
JUNE 29, 2012
Figure 1. Output Load
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
InputTimingReferenceLevels
1.5V
OutputReferenceLevels
1.5V
OutputLoad
See Figure 1
2748 tbl 07
orequivalentcircuit
*Including scope and jig
RESISTOR VALUES FOR
STANDARD TEST LOAD
IOL
R1
R2
24mA
200
Ω
300
Ω
12mA
390
Ω
760
Ω
8mA
600
Ω
1200
Ω
FUNCTIONAL DESCRIPTION:
TheIDT72413,65x5FIFOisdesignedusingadual-portRAMarchitecture
asopposedtothetraditionalshiftregisterapproach. ThisFIFOarchitecturehas
awritepointer,areadpointerandcontrollogic,whichallowsimultaneousread
andwriteoperations.Thewritepointerisincrementedbythefallingedgeofthe
ShiftIn(Sl)control;thereadpointerisincrementedbythefallingedgeoftheShift
Out (SO). The Input Ready (IR) signals when the FIFO has an available
memory location; Output Ready (OR) signals when there is valid data on the
output. OutputEnable(OE)providesthecapabilityofthree-statingtheFIFO
outputs.
FIFO RESET
TheFIFOmustberesetuponpowerupusingtheMasterReset(MR)signal.
ThiscausestheFIFOtoenteranemptystatesignifiedbyOutputReady(OR)
being LOW and Input Ready (IR) being HIGH. In this state, the data outputs
(Q0-4) will be LOW.
DATAINPUT
DataisshiftedinontheLOW-to-HIGHtransitionofShiftIn(Sl). Thisloads
input data into the first word location of the FIFO and causes the lnput Ready
(IR)togoLOW. OntheHlGH-to-LOWtransitionofSI,thewritepointerismoved
tothenextwordpositionand lRgoesHlGHindicatingthereadinesstoaccept
new data. If the FIFO is full, IR will remain LOW until a word of data is shifted
out.
DATAOUTPUT
DataisshiftedoutontheHIGH-to-LOWtransitionofShiftOut(SO).Thiscauses
the internal read pointer to be advanced to the next word location. If data is
present, valid data will appear on the outputs and Output Ready (OR) will go
HIGH.Ifdataisnotpresent,ORwillstayLOWindicatingtheFIFOisempty. The
lastvalidwordreadfromtheFIFOwillremainattheFlFOsoutputwhenitisempty.
WhentheFIFOisnotemptyORgoesLOWontheLOW-to-HlGHtransitionof
SO.
FALL-THROUGHMODE
The FIFO operates in a Fall-Through Mode when data gets shifted into an
emptyFIFO.Afterthefall-throughdelaythedatapropagatestotheoutput.When
the data reaches the output, the Output Ready (OR) goes HIGH.
AFall-ThroughModealsooccurswhentheFIFOis completelyfull. When
dataisshiftedoutofthefullFIFOalocationisavailablefornewdata. Afterafall-
through delay, the lnput Ready goes HlGH. If Shift In is HIGH, the new data
canbewrittentotheFIFO. Thefall-throughdelayofaRAM-basedFIFO(one
clock cycle) is far less than the delay of a Shift register-based FIFO.
SIGNAL DESCRIPTIONS:
INPUTS:
DATA INPUT (D0-4)
Data input lines. The IDT72413 has a 5-bit data input.
R1
30pF*
R2
5V
TEST POINT
2748 drw 03
2K‰
30pF*
5V
OUTPUT
STANDARD TEST LOAD
DESIGN TEST LOAD
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