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參數(shù)資料
| 型號： | IDT72510 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT |
| 中文描述： | 總線匹配雙向FIFO的512 × 18位。 1024 × 9位1024 × 18位。 2048 × 9位 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大小： | 440K |
| 代理商： | IDT72510 |
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5.31
14
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
Port B Interface
Port B also has parity, reread/rewrite and DMA functions.
Port B can be configured to interface to either Intel-style (
R
B
,
W
B
) or Motorola-style (
DS
B
, R/
W
B
) devices in Configuration
Register 5 (see Table 11). Port B can also be configured to talk
to a processor or a peripheral device through Configuration
Register 5. In processor interface mode, the Port B interface
controls are inputs. In peripheral interface mode, the Port B
interface controls are outputs. After a hardware reset or a
software Reset All command, Port B defaults to an Intel-style
processor interface; the controls are inputs.
Two 9-bit words are put together to create each 18-bit word
stored in the internal FIFOs. The first 9-bit word written to Port
B goes into the Odd Byte Register shown in the detailed block
CONFIGURATION REGISTER 5 FORMAT
Bit
0
Select Port B Interface
R
B
&
W
B
or
DS
B
& R/
W
B
1
Byte Order of 18-bit Word
Function
0
1
Pins are
R
B
and
W
B
(Intel-style interface)
Pins are
DS
B
and R/
W
B
(Motorola-style interface)
Lower byte D
A7
-D
A0
and parity D
A16
are read or written first on Port
B
0
1
Upper byte D
A15
-D
A8
and parity D
A17
are read or written first on
Port B
2
Full Flag Definition
0
Full Flag is asserted when write pointer meets read pointer
1
Full Flag is asserted when write pointer meets reread pointer
3
Empty Flag Definition
0
1
Empty Flag is asserted when read pointer meets write pointer
Empty Flag is asserted when read pointer meets rewrite pointer
4
REQ Pin Polarity
0
REQ pin active HIGH
1
REQ pin active LOW
5
ACK Pin Polarity
0
1
ACK pin active LOW
ACK pin active HIGH
00
2 internal clocks between REQ assertion and ACK assertion
7-6
REQ / ACK Timing
01
3 internal clocks between REQ assertion and ACK assertion
10
4 internal clocks between REQ assertion and ACK assertion
11
5 internal clocks between REQ assertion and ACK assertion
8
Port B Read and Write
Timing Control for Peripheral Mode
0
1
R
B
,
W
B
, and
DS
B
are asserted for 1 internal clock
R
B
,
W
B
, and
DS
B
are asserted for 2 internal clocks
internal clock = CLK
9
Internal Clock
0
Frequency Control
1
internal clock = CLK divided by 2
10
Port B Interface
Mode Control
0
1
Processor interface mode (Port B controls are inputs)
Peripheral interface mode (Port B controls are outputs)
00
Stand-alone mode (18- to 9-bits, 36- to 18-bits)
12-11
Width Expansion
01
Reserved
Mode Control
10
Slave width expansion mode (36- to 9-bits)
11
Master width expansion mode (36- to 9-bits)
13
Unused
14
Unused
15
Unused
2669 tbl 15
Table 11. BiFIFO Configuration Register 5 Format
diagram. The Odd Byte Register valid bit (Bit 8) in the Status
Register is
1
when this first 9-bit word is written. The data bits
from Port B (D
B0
-D
B7
) are also stored in the lower 8 bits of the
Status Register when Status Register format 0 is selected
(see Table 8). The second write on Port B moves the 9-bits
from Port B and the 9-bits in the Odd Byte Register into the
B
→
A FIFO and advances the B
→
A Write Pointer. The Status
Register valid bit is set to
0
after the second write.
When Port B reads data from the A
→
B FIFO, two buffers
choose which 9 of the 18 memory bits are sent to Port B.
These buffers alternate between the upper 9 bits (D
A8
-D
A15
,
D
A17
) and the lower 9 bits (D
A0
-D
A7
, D
A16
). The A
→
B Read
Pointer is advanced after every two Port B reads.
The BiFIFO can be set to order the 9-bit data so the first 9-
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| IDT72510L35J | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72605L20J | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72605L20J8 | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72605L20PF | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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