參數(shù)資料
型號: IDT72511
廠商: Integrated Device Technology, Inc.
英文描述: High-Performance Current-Mode PWM Controller 8-SOIC 0 to 70
中文描述: 雙向并行FIFO的512 × 18
文件頁數(shù): 1/28頁
文件大?。?/td> 434K
代理商: IDT72511
Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DECEMBER 1995
1996 Integrated Device Technology, Inc.
DSC-2668/6
5.32
1
FEATURES:
Two side-by-side FIFO memory arrays for bidirectional
data transfers
512 x 18-Bit - 512 x 18-Bit (IDT72511)
1024 x 18-Bit - 1024 x 18-Bit (IDT72521)
18-bit data buses on Port A side and Port B side
Can be configured for 18-to-18-bit or 36-to-36-bit com-
munication
Fast 35ns access time
Fully programmable standard microprocessor interface
Built-in bypass path for direct data transfer between two
ports
Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
Two programmable flags, Almost-Empty and Almost-Full
for each FIFO
Programmable flag offset can be set to any depth in the
FIFO
Any of the eight flags can be assigned to four external
flag pins
Flexible reread/rewrite capabilities
Six general-purpose programmable I/O pins
Standard DMA control pins for data exchange with
peripherals
68-pin PGA and PLCC packages
DESCRIPTION:
The IDT72511 and IDT72521 are highly integrated first-in,
first-out memories that enhance processor-to-processor and
processor-to-peripheral communications. IDT BiFIFOs inte-
grate two side-by-side memory arrays for data transfers in
two directions.
The BiFIFOs have two ports, A and B, that both have
standard microprocessor interfaces. All BiFIFO operations
are controlled from the 18-bit wide Port A. Port B is also 18
bits wide and can be connected to another processor or a
peripheral controller. The BiFIFOs have a 9-bit bypass path
that allows the device connected to Port A to pass messages
directly to the Port B device.
Ten registers are accessible through Port A, a Com-
mand Register, a Status Register, and eight Configuration
Registers.
The IDT BiFIFO has programmable flags. Each FIFO
memory array has four internal flags, Empty, Almost-Empty,
Almost-Full and Full, for a total of eight internal flags. The
Almost-Empty and Almost-Full flag offsets can be set to any
depth through the Configuration Registers. These eight inter-
nal flags can be assigned to any of four external flag pins
(FLG
A
-FLG
D
) through one Configuration Register.
Port B has programmable I/O, reread/rewrite and DMA
functions. Six programmable I/O pins are manipulated through
PARALLEL BIDIRECTIONAL FIFO
512 x 18 & 1024 x 18
IDT72511
IDT72521
SIMPLIFIED BLOCK DIAGRAM
Data
Data
Control
Flags
Control
DMA
Processor
Interface
A
Programmable
Flag Logic
Port
B
Port
A
Bypass
18-bits
9-bits
2668 drw 01
18-Bit
FIFO
Registers
Handshake
Interface
Processor
Interface
B
Programmable
I/O Logic
I/O
18-bits
18-Bit
FIFO
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
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