參數(shù)資料
型號: IDT72510L35J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Current-Mode PWM Controller 8-PDIP 0 to 70
中文描述: 512 X 18 BI-DIRECTIONAL FIFO, 35 ns, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 11/32頁
文件大?。?/td> 440K
代理商: IDT72510L35J
5.31
11
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
RESET COMMAND FUNCTIONS
SELECT CONFIGURATION REGISTER
COMMAND FUNCTIONS
Reset
Operands
000
001
Function
No Operation
Reset B
A FIFO (Read, Write, and Rewrite
Pointers = 0)
010
Reset A
B FIFO (Read, Write, and Reread
Pointers = 0)
011
Reset B
A and A
B FIFO
100
101
110
111
Reset Internal DMA Request Circuitry
No Operation
No Operation
Reset All
Operands
000
Function
Select Configuration Register 0
001
Select Configuration Register 1
010
011
Select Configuration Register 2
Select Configuration Register 3
100
101
Select Configuration Register 4
Select Configuration Register 5
110
111
Select Configuration Register 6
Select Configuration Register 7
2669 tbl 07
Table 4. Select Configuration Register Command Functions.
DMA DIRECTION COMMAND FUNCTIONS
Operands
XX0
XX1
Function
Write B
A FIFO
Read A
B FIFO
2669 tbl 08
Table 5. Set DMA Direction Command Functions. Command Only
Operates in Peripheral Interface Mode
STATUS REGISTER FORMAT COMMAND
FUNCTIONS
Operands
XX0
XX1
Function
Status Register Format 0
Status Register Format 1
2669 tbl 09
Table 6. Command Functions to Set the Status Register Format
2669 tbl 06
Table 3. Reset Command Functions
STATE AFTER RESET
Hardware Reset
(
RS
asserted)
Software Reset
B
A and
A
B (011)
B
A (001)
A
B (010)
Internal
Request
(100)
All (111)
Configuration Registers 0-3
0000H
0000H
Configuration Register 4
Configuration Register 5
6420H
0000H
6420H
0000H
Configuration Register 7
0000H
0000H
Status Register format
B
A Read, Write, Rewrite
Pointers
A
B Read, Write, Reread
Pointers
Odd byte register valid bit
0
0
0
0
0
0
0
0
0
clear
clear
clear
clear
DMA direction
B
A write
clear
clear
DMA internal request
Parity errors
clear
clear
2669 tbl 10
Table 7. The BiFIFO State After a Reset Command
6420
H
, and Configuration Registers 5 and 7 are
0000
H
.
Additionally, Status Register format 0 is selected, all the
pointers including the Reread and Rewrite Pointers are set to
0
, the odd byte register valid bit is cleared, the DMA direction
is set to B
A write, the internal DMA request circuitry is
cleared (set to its initial state), and all parity errors are cleared.
A software reset command can reset A
B pointers and
the B
A pointers to
0
independently or together. The request
(REQ) DMA circuitry can also be reset independently. A
software Reset All command resets all the pointers, the DMA
request circuitry, and sets all the Configuration Registers to
their default condition. Note that a hardware reset is
NOT
the
same as a software Reset All command. Table 7 shows the
BiFIFO state after the different hardware and software resets.
相關(guān)PDF資料
PDF描述
IDT72510L50J High-Performance Current-Mode PWM Controller 14-SOIC 0 to 70
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