參數(shù)資料
型號: IDT72510L35J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Current-Mode PWM Controller 8-PDIP 0 to 70
中文描述: 512 X 18 BI-DIRECTIONAL FIFO, 35 ns, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 6/32頁
文件大?。?/td> 440K
代理商: IDT72510L35J
5.31
6
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
IDT’s BiFIFO family is versatile for both multiprocessor
and peripheral applications. Data can be sent through both
FIFO memories concurrently, thus freeing both processors
from laborious direct memory access (DMA) protocols and
frequent interrupts.
Two full 18-bit wide FIFOs are integrated into the IDT
BiFIFO, making simultaneous data exchange possible. Each
FIFO is monitored by separate internal read and write point-
ers, so communication is not only bidirectional, it is also
totally independent in each direction. The processor con-
nected to Port A of the BiFIFO can send or receive mes-
sages directly to the Port B device using the BiFIFO’s 9-bit
bypass path.
The BiFIFOs can be used in three different bus configura-
tions: 18 bits to 9 bits, 36 bits to 9 bits and 36 bits to 18 bits.
One BiFIFO can be used for the 18- to 9-bit configuration,
and two BiFIFOs are required for 36- to 9-bit or 36- to 18-bit
configurations. Bits 11 and 12 of Configuration Register 5
determine the BiFIFO configuration (see Table 11 for
Configuration Register 5 format).
36-BIT PROCESSOR to 18-BIT PROCESSOR CONFIGURATION
Processor
A
Address
Data
C
L
RAM
Control
36
Processor
B
Data
RAM
C
L
Control
18
2669 drw 04
IDT
BiFIFO
(Stand-Alone)
Cntl A
Data A Data B
Cntl B
ACK
REQ
CLK
IDT
BiFIFO
(Stand-Alone)
Cntl A
Data AData B
Cntl B
1
3
18
ACK
REQ
CLK
9
The microprocessor or microcontroller connected to Port
A controls all operations of the BiFIFOs. Thus, all Port A
interface pins are inputs driven by the controlling processor.
Port B can be programmed to interface either with a second
processor or a peripheral device. When Port B is programmed
in processor interface mode, the Port B interface pins are
inputs driven by the second processor. If a peripheral device
is connected to the BiFIFOs, Port B is programmed to pe-
ripheral interface mode and the interface pins are outputs.
18- to 9-bit Configurations
A single BiFIFO can be configured to connect an 18-bit
processor to another 9-bit processor or a 9-bit peripheral.
Bits 11 and 12 of Configuration Register 5 should be set to
00
for a stand-alone configuration. Figures 1 and 2 show the
BiFIFO in 18- to 9-bit configurations for processor and
peripheral interface modes respectively.
36- to 9-bit Configurations
Two BiFIFOs can be hooked together to create a 36-bit to
9-bit configuration. This means that a 36-bit processor can
Figure 1. 36- to 18-Bit Processor Interface Configuration
NOTE:
1. Upper BiFIFO only is used in 18- to 9-bit configuration. Note that
Cntl A
refers to
CS
A,
A
1
, A
0
, R/
W
A a
nd
DS
A;
Cntl B
refers to R/
W
B
and
DS
B
or
R
B
and
W
B
.
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