參數(shù)資料
型號(hào): IDT72520L25J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT
中文描述: 1K X 18 BI-DIRECTIONAL FIFO, 25 ns, PQCC52
封裝: PLASTIC, LCC-52
文件頁(yè)數(shù): 13/32頁(yè)
文件大?。?/td> 440K
代理商: IDT72520L25J
5.31
13
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
CONFIGURATION REGISTER FORMATS
15
Config. Reg. 0
Config. Reg. 1
Config. Reg. 2
Config. Reg. 3
Config. Reg. 4
Config. Reg. 5
Config. Reg. 6
Config. Reg. 7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A
B FIFO Almost-Empty Flag Offset
A
B FIFO Almost-Full Flag Offset
B
A FIFO Almost-Empty Flag Offset
B
A FIFO Almost-Full Flag Offset
Flag D Pin Assignment
Flag C Pin Assignment
Flag B Pin Assignment
Flag A Pin Assignment
General Control
Reserved
Parity Control
15
15
15
15
15
15
15
10
10
10
10
9
9
9
9
12
11
8
7
4
3
0
0
0
0
0
0
0
0
checking is enabled for data read and written through Port B.
Bit 8 controls parity checking and generation for B
A write data.
Bit 9 controls parity checking and generation for A
B read data.
Bit 10 controls whether the parity is odd or even. Bit 11 is used
to assign the internal parity checking error to the FLG
A
pin.
When the parity error is assigned to FLG
A
, the Configuration
Register 4 flag assignment for FLG
A
is ignored.
Programmable Flags
The IDT BiFIFO has eight internal flags; four of these flags
have programmable offsets, the other four are empty or full.
Associated with each FIFO memory array are four internal
flags, Empty, Almost-Empty, Almost-Full and Full, for the total
of eight internal flags. The Almost-Empty and Almost-Full
offsets can be set to any depth through the Configuration
Registers 0-3 (see Table 9). The offset (or depth) of FIFO RAM
array is based on the unit of an 18-bit word. The flags are
asserted at the depths shown in Table 13. After a hardware
reset or a software reset all, the almost flag offsets are set to
0
. Even though the offsets are equivalent, the Empty and
Almost-Empty flags have different timing which means that
the flags are not coincident. Similarly, the Full and Almost-Full
flags are not coincident because of timing.
These eight internal flags can be assigned to any of four
external flag pins (FLG
A
-FLG
D
) through Configuration Reg-
ister 4 (see Table 10). For the specific flag timings, see
Figures 20-23.
The current state of all eight flags is available in the Status
Register in Status Register format 1. In Status Register format
0, only four flags can be found in the Status Register (see
Table 8).
EXTERNAL FLAG ASSIGNMENT CODES
Assignment
Code
Internal Flag Assigned to Flag Pin
0000
A
B
Empty
0001
A
B
Almost-Empty
0010
A
B
Full
0011
A
B
Almost-Full
0100
B
A
Empty
0101
B
A
Almost-Empty
0110
B
A
Full
0111
B
A
Almost-Full
1000
A
B Empty
1001
A
B Almost-Empty
1010
A
B Full
1011
A
B Almost-Full
1100
B
A Empty
1101
B
A Almost-Empty
1110
B
A Full
1111
B
A Almost-Full
2669 tbl 14
Table 10. Configuration Register 4 Internal Flag Assignments to
External Flag Pins.
NOTE:
1. Bit 9 of Configuration Registers 0-3 must be set to 0 on the IDT72510.
2669 tbl 13
Table 9. The BiFIFO Configuration Register Formats
相關(guān)PDF資料
PDF描述
IDT72520L35J BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT
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IDT72510 BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT
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