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參數(shù)資料
| 型號： | IDT72520L50J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT |
| 中文描述： | 1K X 18 BI-DIRECTIONAL FIFO, 50 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 7/32頁 |
| 文件大小： | 440K |
| 代理商： | IDT72520L50J |
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5.31
7
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
36-BIT PROCESSOR to 18-BIT PERIPHERAL CONFIGURATION
Figure 2. 36- to 18-Bit Peripheral Interface Configuration
NOTE:
1. Upper BiFIFO only is used in 18- to 9-bit configuration. Note that
Cntl A
refers to
CS
A, A
1
, A
0
,
R/
W
A
a
nd
DS
A;
Cntl B
refers to R/
W
B
and
DS
B
or
R
B
and
W
B
.
IDT
BiFIFO
(Stand-Alone)
Cntl A
Processor
Peripheral
Controller
Data
Data A Data B
Data
Cntl B
ACK
REQ
CLK
Address
ACK
REQ
Cntl
I/O
Data
IDT
BiFIFO
(Stand-Alone)
Cntl A
Data A Data B
Cntl B
ACK
REQ
CLK
C
L
RAM
1
3
18
DMA or System
Clock
Control
18
9
36
2669 drw 05
talk to a 9-bit processor or a 9-bit peripheral. Both BiFIFOs
are programmed simultaneously through Port A by placing
one command word on the most significant 16 data bits and
one command word on the least significant 16 data bits
(parity bits should be ignored).
One BiFIFO must be programmed as the master device
and the other BiFIFO is the slave device. Bits 11 and 12 of
Configuration Register 5 are set to
10
for the slave device
and
11
for the master device. The first two 9-bit words on
Port B are read from or written to the slave device and the
next two 9-bit words go to the master device.
When both BiFIFOs are in peripheral interface mode, the
Port B interface pins of the master device are outputs and
this BiFIFO controls the bus. The Port B interface pins of the
slave device are inputs driven by the master BiFIFO. Two
BiFIFOs are connected in Figure 4 to create a 36- to 9-bit
peripheral interface.
The two BiFIFOs shown in Figure 3 are configured to
connect a 36-bit processor to a 9-bit processor.
36- to 18-bit Configurations
In a 36- to 18-bit configuration, two BiFIFOs operate in
parallel. Both BiFIFOs are programmed simultaneously, 16
data bits to each device with the 4 parity bits ignored.
Both BiFIFOs must be programmed into stand-alone mode
for a 36-bit processor to communicate with an 18-bit proces-
sor or an 18-bit peripheral. This means that bits 11 and 12 of
Configuration Register 5 must be set to
00
.
This configuration can be extended to wider bus widths
(54- to 27-bits, 72- to 36-bits, …) by adding more BiFIFOs to
the configuration. Figures 1 and 2 show multiple BiFIFOs
configured for processor and peripheral interface modes
respectively.
Processor Interface Mode
When a microprocessor or microcontroller is connected to
Port B, all BiFIFOs in the configuration must be programmed
to processor interface mode. In this mode, all Port B interface
controls are inputs. Both REQ and CLK pins should be pulled
LOW to ensure that the set-up and hold time requirements for
these pins are met during reset. Figures 1 and 3 show
BiFIFOs in processor interface mode.
Peripheral Interface Mode
If Port B is connected to a peripheral controller, all BiFIFOs
in the configuration must be programmed in the peripheral
interface mode. To assure fixed high states for
R
B
and
W
B
before they are programmed into an output, both pins should
be pulled-up to V
CC
with 10K resistors.
If the BiFIFOs are in stand-alone configuration mode
(18- to 9-bit, 36- to 18-bit, …), then the Port B interface pins are
all outputs. Of course, only one set of Port B interface pins
should be used to control a single peripheral device, while the
other interface pins are all ignored. Figure 2 shows stand-
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| IDT72605L20J | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72605L20J8 | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72605L20PF | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72605L20PF8 | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72605L25J | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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