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參數(shù)資料
| 型號： | IDT72805LB25PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 24/26頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC DUAL 256X18 128TQFP |
| 標準包裝： | 72 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 4.6K（256 x 18） |
| 數(shù)據(jù)速率： | 40MHz |
| 訪問時間： | 25ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 72805LB25PF |
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
JANUARY 13, 2009
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72805LB/72815LB/72825LB/72835LB/72845LB support two
different timing modes of operation. The selection of which mode will
operate is determined during configuration at Reset (
RS). During a RS
operation, the First Load (
FL), Read Expansion Input ( RXI) and Write
Expansion Input (
WXI) pins are used to select the timing mode per the truth
table shown in Table 3. In IDT Standard Mode, the first word written to an
empty FIFO will not appear on the data output lines unless a specific read
operation is performed. A read operation, which consists of activating Read
Enable (
REN) and enabling a rising Read Clock (RCLK) edge, will shift the
word from internal memory to the data output lines. In FWFT mode, the first
word written to an empty FIFO is clocked directly to the data output lines
after three transitions of the RCLK signal. A
REN does not have to be
asserted for accessing the first word.
Various signals, both input and output signals operate differently de-
pending on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags,
FF, PAF, HF, PAE and EF operate in the
manner outlined in Table 1. To write data into to the FIFO, Write Enable
(
WEN) must be LOW. Data presented to the DATA IN lines will be clocked
into the FIFO on subsequent transitions of the Write Clock (WCLK). After the
first write is performed, the Empty Flag (
EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty
flag (
PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where n is the Empty offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (
HF) would toggle to LOW
once the 129th (IDT72805LB), 257th (IDT72815LB), 513th (IDT72825LB),
1,025th (IDT72835LB), and 2,049th (IDT72845LB) word respectively was
written into the FIFO. Continuing to write data into the FIFO will cause the
Programmable Almost-Full flag (
PAF) to go LOW. Again, if no reads are
performed, the
PAF will go LOW after (256-m) writes for the IDT72805LB,
(512-m) writes for the IDT72815LB, (1,024-m) writes for the IDT72825LB,
(2,048–m) writes for the IDT72835LB and (4,096–m) writes for the
IDT72845LB. The offset “m” is the Full offset value. This parameter is also
user programmable. See section on Programmable Flag Offset Loading. If
there is no Full offset specified, the
PAF will be LOW when the device is 31
away from completely full for IDT72805LB, 63 away from completely full for
IDT72815LB, and 127 away from completely full for the IDT72825LB/
72835LB/72845LB.
When the FIFO is full, the Full Flag (
FF) will go LOW, inhibiting further
write operations. If no reads are performed after a reset,
FF will go LOW
after D writes to the FIFO. D = 256 writes for the IDT72805LB, 512 for the
IDT72815LB, 1,024 for the IDT72825LB, 2,048 for the IDT72835LB and
4,096 for the IDT72845LB, respectively.
If the FIFO is full, the first read operation will cause
FF to go HIGH.
Subsequent read operations will cause
PAF and the Half-Full flag (HF) to
go HIGH at the conditions described in Table 1. If further read operations
occur, without write operations, the Programmable Almost-Empty flag
(
PAE) will go LOW when there are n words in the FIFO, where n is the Empty
offset value. If there is no Empty offset specified, the
PAE will be LOW when
the device is 31 away from completely empty for IDT72805LB, 63 away from
completely empty for IDT72815LB, and 127 away from completely empty
for IDT72825LB/72835LB/72845LB. Continuing read operations will cause
the FIFO to be empty. When the last word has been read from the FIFO, the
EF will go LOW inhibiting further read operations. REN is ignored when the
FIFO is empty.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags,
IR, PAF, HF, PAE and OR operate in the
manner outlined in Table 2. To write data into to the FIFO,
WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of WCLK. After the first write is performed, the
Output Ready (
OR) flag will go LOW. Subsequent writes will continue to fill
up the FIFO.
PAE will go HIGH after n + 2 words have been loaded into the
FIFO, where n is the Empty offset value. The default setting for this value
is stated in the footnote of Table 2. This parameter is also user program-
mable. See section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the
HF would toggle to LOW once the 130th
(72805LB), 258th (72815LB), 514th (72825LB), 1,026th (72835LB), and
2,050th (72845LB) word respectively was written into the FIFO. Continuing
to write data into the FIFO will cause the
PAF to go LOW. Again, if no reads
are performed, the
PAFwillgoLOWafter(257-m)writesfortheIDT72805LB,
(513-m) writes for the IDT72815LB, (1,025-m) writes for the IDT72825LB,
(2,049–m) writes for the IDT72835LB and (4,097–m) writes for the
IDT72845LB, where m is the Full offset value. The default setting for this
value is stated in the footnote of Table 2.
When the FIFO is full, the Input Ready (
IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset,
IR will go
HIGH after D writes to the FIFO. D = 257 writes for the IDT72805LB, 513
for the IDT72815LB, 1,025 for the IDT72825LB, 2,049 for the IDT72835LB
and 4,097 for the IDT72845LB. Note that the additional word in FWFT mode
is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the
IR flag to go LOW.
Subsequent read operations will cause the
PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the
PAE will go LOW when there are n + 1 words in the
FIFO, where n is the Empty offset value. If there is no Empty offset specified,
the
PAE will be LOW when the device is 32 away from completely empty for
IDT72805LB, 64 away from completely empty for IDT72815LB, and 128
away from completely empty for IDT72825LB/72835LB/72845LB. Continu-
ing read operations will cause the FIFO to be empty. When the last word has
been read from the FIFO,
OR will go HIGH inhibiting further read operations.
REN is ignored when the FIFO is empty.
PROGRAMMABLE FLAG LOADING
Full and Empty flag Offset values can be user programmable. The
IDT72805LB/72815LB/72825LB/72835LB/72845LB has internal registers
for these offsets. Default settings are stated in the footnotes of Table 1 and
Table 2. Offset values are loaded into the FIFO using the data input lines D0-
D11. To load the offset registers, the Load (
LD) pin and WEN pin must be
held LOW. Data present on D0-D11 will be transferred in to the Empty Offset
register on the first LOW-to-HIGH transition of WCLK. By continuing to hold
the
LD and WEN pin low, data present on D0-D11 will be transferred into the
Full Offset register on the next transition of the WCLK. The third transition
again writes to the Empty Offset register. Writing all offset registers does not
have to occur at one time. One or two offset registers can be written and then
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| IDT72805LB25PF8 | 功能描述:IC FIFO SYNC DUAL 256X18 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT7280L12PA | 功能描述:IC MEM FIFO 256X9 12NS 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
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| IDT7280L12PAG | 功能描述:IC MEM FIFO 256X9 12NS 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
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