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參數(shù)資料
| 型號： | IDT72851L25PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 4096X18 25NS 64QFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 72K（4K x 18） |
| 數(shù)據(jù)速率： | 40MHz |
| 訪問時間： | 25ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72851L25PF8 |
6
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
MARCH 2013
When either of the two Read Enable RENA1, RENA2 (RENB1, RENB2)
associatedwithFIFOA(B)isHIGH,theoutputregisterholdsthepreviousdata
and no new data is allowed to be loaded into the register.
WhenallthedatahasbeenreadfromFIFOA(B),theEmptyFlagEFA(EFB)
willgoLOW,inhibitingfurtherreadoperations. Onceavalidwriteoperationhas
been accomplished, EFA(EFB) will go HIGH after tREF and a valid read can
begin. TheReadEnablesRENA1,RENA2(RENB1,RENB2)areignoredwhen
FIFO A (B) is empty.
OutputEnable(OEA,OEB)—WhenOutputEnableOEA(OEB)isenabled
(LOW),theparalleloutputbuffersofFIFOA(B)receivedatafromtheirrespective
outputregister. WhenOutputEnable OEA(OEB)isdisabled(HIGH),theQA
(QB) output data bus is in a high-impedance state.
Write Enable 2/Load (WENA2/LDA, WENB2/LDB) — This is a dual-
purpose pin. FIFO A (B) is configured at Reset to have programmable flags
or to have two write enables, which allows depth expansion. If WENA2/LDA
(WENB2/LDB) issetHIGHatResetRSA=LOW(RSB = LOW),thispinoperates
as a second write enable pin.
If FIFO A (B) is configured to have two write enables, when Write Enable
1WENA1(WENB1)isLOWandWENA2/LDA(WENB2/LDB)isHIGH,datacanbe
loaded into the input register and RAM array on the LOW-to-HIGH transition
ofeveryWriteClockWCLKA(WCLKB). Dataisstoredinthearraysequentially
and independently of any ongoing read operation.
Inthisconfiguration,whenWENA1(WENB1)isHIGHand/orWENA2/LDA
(WENB2/LDB)isLOW,theinputregisterofArrayAholdsthepreviousdataand
no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag FFA(FFB) will go LOW, inhibiting
furtherwriteoperations. Uponthecompletionofavalidreadcycle,FFA(FFB)
willgoHIGHaftertWFF,allowingavalidwritetobegin. WENA1,(WENB1)and
WENA2/LDA(WENB2/LDB) are ignored when the FIFO is full.
FIFO A (B) is configured to have programmable flags when the WENA2/
LDA(WENB2/LDB)issetLOWatResetRSA = LOW(RSB=LOW). EachFIFO
containsfour8-bitoffsetregisterswhichcanbeloadedwithdataontheinputs,
orreadontheoutputs. SeeFigure3fordetailsofthesizeoftheregistersand
thedefaultvalues.
If FIFO A (B) is configured to have programmable flags, when the WENA1
(WENB1) and WENA2/LDA(WENB2/LDB) are set LOW, data on the DA (DB)
inputsarewrittenintotheEmpty(LeastSignificantBit)Offsetregisteronthefirst
LOW-to-HIGH transition of the WCLKA (WCLKB). Data are written into the
Empty (Most Significant Bit) Offset register on the second LOW-to-HIGH
transitionofWCLKA(WCLKB),intotheFull(LeastSignificantBit)Offsetregister
on the third transition, and into the Full (Most Significant Bit) Offset register on
thefourthtransition. ThefifthtransitionofWCLKA(WCLKB)againwritestothe
Empty(LeastSignificantBit)Offsetregister.
However,writingalloffsetregistersdoesnothavetooccuratonetime. One
ortwooffsetregisterscanbewrittenandthenbybringingLDA(LDB)HIGH,FIFO
A (B) is returned to normal read/write operation. When LDA(LDB) is set LOW,
andWENA1(WENB1)isLOW,thenextoffsetregisterinsequenceiswritten.
ThecontentsoftheoffsetregisterscanbereadontheQA(QB)outputs when
WENA2/LDA(WENB2/LDB)issetLOWandbothReadEnablesRENA1,RENA2
(RENB1,RENB2)aresetLOW. DatacanbereadontheLOW-to-HIGHtransition
of the Read Clock RCLKA (RCLKB).
SIGNAL DESCRIPTIONS
FIFOAandFIFOBareidenticalineveryrespect.Thefollowingdescription
explainstheinteractionofinputandoutputsignalsforFIFOA.Thecorrespond-
ing signal names for FIFO B are provided in parentheses.
INPUTS:
Data In (DA0 – DA8, DB0 – DB8)
— DA0 - DA8 are the nine data inputs
for memory array A. DB0 - DB8 are the nine data inputs for memory array B.
CONTROLS:
Reset
(RSA,RSB)—ResetofFIFOA(B)isaccomplishedwheneverRSA
(RSB)inputistakentoaLOWstate.DuringReset,theinternalreadandwrite
pointersassociatedwiththeFIFOaresettothefirstlocation.AResetisrequired
afterpower-upbeforeawriteoperationcantakeplace. TheFullFlagFFA(FFB)
and Programmable Almost-Full flag PAFA(PAFB) will be reset to HIGH after
tRSF. TheEmptyFlagEFA(EFB)andProgrammableAlmost-EmptyflagPAEA
(PAEB) will be reset to LOW after tRSF. During Reset, the output register is
initializedtoallzerosandtheoffsetregistersareinitializedtotheirdefaultvalues.
Write Clock (WCLKA, WCLKB) — A write cycle to Array A (B) is
initiated on the LOW-to-HIGH transition of WCLKA (WCLKB). Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of
WCLKA (WCLKB). The Full Flag FFA(FFB) and Programmable Almost-Full
flagPAFA(PAFB)aresynchronizedwithrespecttotheLOW-to-HIGHtransition
oftheWriteClockWCLKA(WCLKB).
The Write and Read Clocks can be asynchronous or coincident.
Write Enable 1 (WENA1, WENB1) — If FIFO A (B) is configured for
programmable flags, WENA1 (WENB1) is the only enable control pin. In this
configuration,whenWENA1(WENB1)isLOW,datacanbeloadedintotheinput
registerofRAMArrayA(B)ontheLOW-to-HIGHtransitionofeveryWriteClock
WCLKA(WCLKB). DataisstoredinArrayA(B)sequentiallyandindependently
of any ongoing read operation.
Inthisconfiguration,whenWENA1(WENB1)isHIGH,theinputregisterholds
the previous data and no new data is allowed to be loaded into the register.
IftheFIFOisconfiguredtohavetwowriteenables,whichallowsfordepth
expansion. See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow, FFA (FFB) will go LOW, inhibiting further write
operations. Uponthecompletionofavalidreadcycle,theFFA(FFB)willgoHIGH
aftertWFF,allowingavalidwritetobegin. WENA1(WENB1)isignoredwhenFIFO
A (B) is full.
Read Clock (RCLKA, RCLKB) — Data can be read from Array A (B) on
theLOW-to-HIGHtransitionofRCLKA(RCLKB). TheEmptyFlag EFA(EFB)
andProgrammableAlmost-EmptyFlagPAEA(PAEB)aresynchronizedwith
respect to the LOW-to-HIGH transition of RCLKA (RCLKB).
The Write and Read Clocks can be asynchronous or coincident.
Read Enables (RENA1, RENA2, RENB1, RENB2) — When both Read
Enables RENA1, RENA2 (RENB1, RENB2) are LOW, data is read from Array
A (B) to the output register on the LOW-to-HIGH transition of the Read Clock
RCLKA (RCLKB).
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| IDT72851L25PFI | 功能描述:IC FIFO SYNC 4096X18 25NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72851L25PFI8 | 功能描述:IC FIFO SYNC 4096X18 25NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72851L25TF | 功能描述:IC FIFO SYNC DUAL 8192X9 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72851L25TF8 | 功能描述:IC FIFO SYNC DUAL 8192X9 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72851L25TFI | 功能描述:IC FIFO SYNC DUAL 8192X9 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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