參數(shù)資料
型號(hào)： IDT7290820J8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 26/27頁(yè)
文件大?。?/td> 0K
描述： IC DGTL SW 2048X2048 84-PLCC
標(biāo)準(zhǔn)包裝： 200
系列： 7200
類型： 多路復(fù)用器
電路： 1 x 16:16
獨(dú)立電路： 1
電壓電源： 單電源
電源電壓： 4.75 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC（29.21x29.21）
包裝： 帶卷 (TR)
其它名稱： 7290820J8
8
COMMERCIALTEMPERATURERANGE
IDT7290820 5V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
CONSTANT DELAY MODE (
V/C BIT = 1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT7290820, the minimum throughput delay achievable in the constant
delay mode will be one frame. For example, in 2.048 Mb/s mode, when input
time-slot31isswitchedtooutputtime-slot0.Themaximumdelayof94time-slots
ofdelayoccurswhentime-slot0inaframeisswitchedtotime-slot31intheframe.
See Table 3.
MICROPROCESSOR INTER.ACE
The IDT7290820 provides a parallel microprocessor interface for multi-
plexed or non-multiplexed bus structures. This interface is compatible with
Motorola non-multiplexed and multiplexed buses.
If the IM pin is low a Motorola non-multiplexed bus should be connected to
the device. If the IM pin is high, the device monitors the AS/ALE and DS/
RD to
determine what mode the IDT7290820 should operate in.
If DS/
RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed
timing is selected. If DS/
RDishighattherisingedgeofAS/ALE,thenthemode
2 multiplexed bus timing is selected.
For multiplexed operation, the required signals are the 8-bit data and
address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch
enable (AS/ ALE), Data strobe/Read (DS/
RD),Read/Write/Write(R/W/WR),
Chip select (
CS) and Data transfer acknowledge (DTA). See Figure 12 and
Figure 13 for multiplexed parallel microport timing.
For the Motorola non-multiplexed bus, the required signals are the 16-bit
data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines
(
CS, DS, R/W and DTA). See Figure 14 and 15 for Motorola non-multiplexed
microporttiming.
The IDT7290820 microport provides access to the internal registers,
connectionanddatamemories.Alllocationsprovideread/writeaccessexcept
for the data memory and the frame alignment register which are read only.
MEMORY MAPPING
The address bus on the microprocessor interface selects the internal
registers and memories of the IDT7290820.
If the A7 address input is low, then A6 through A0 are used to address the
interfacemodeselection(IMS),control(CR),framealignment(FAR)andframe
input offset (FOR) registers (Table 4). If the A7 is high, then A6 through A0 are
used to select 32, 64, or 128 locations corresponding to data rate of the
ST-BUS. The address input lines and the stream address bits (STA) of the
control register allow access to the entire data and connection memories. The
control and IMS registers together control all the major functions of the device,
see Figure 3.
As explained in the Serial Data Interface Timing and Switching Configura-
tionssections,aftersystempower-up,theIMSregistershouldbeprogrammed
immediatelytoestablishthedesiredswitchingconfiguration.
The data in the control register consists of the memory block programming
bit (MBP), the memory select bit (MS) and the stream address bits (STA). As
explained in the Memory Block Programming section, the MBP bit allows the
entire connection memory block to be programmed. The memory select bit is
used to designate the connection memory or the data Memory. The stream
addressbitsselectinternalmemorysubsectionscorrespondingtoinputoroutput
serialstreams.
The data in the IMS register consists of block programming bits (BPD0-
BPD4), block programming enable bit (BPE), output stand by bit (OSB), start
frame evaluation bit (SFE) and data rate selection bits (DR0-1). The block
programming and the block programming enable bits allows users to program
theentireconnectionmemory(seeMemoryBlockProgrammingsection).Ifthe
ODE pin is low, the OSB bit enables (if high) or disables (if low) all ST-BUS
output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and
all TX output drivers are enabled.
CONNECTION MEMORY CONTROL
The CCO pin is a 4.096, 8.192 or 16.384 Mb/s output, which carries 512,
1,024or2,048bits,respectively.ThecontentsoftheCCObitofeachconnection
memory location are output on the CCO pin once every frame. The contents
oftheCCObitsoftheconnectionmemoryaretransmittedsequentiallyontothe
CCO pin and are synchronous with the data rates on the other serial streams.
The CCO bit is output one channel before the corresponding channel on
the serial streams. For example, in 2.048 Mb/s mode (32 channels per frame),
the contents of the CCO bit in position 0 (TX0, CH0) of the connection memory
is output on the first clock cycle of channel 31 through CCO pin. The contents
of the CCO bit in position 32 (TX1, CH0) of the connection memory is output on
the second clock cycle of channel 31 via CCO pin.
If the ODE pin or the OSB bit is high, the OE bit of each connection memory
location controls the output drivers-enables (if high) or disables (if low). See
Table 5 for detail.
Theprocessorchannel(PC)bitoftheconnectionmemoryselectsbetween
Processor Mode and Connection Mode. If high, the contents of the connection
memoryareoutputontheTXstreams. Iflow,thestreamaddressbit(SAB)and
the channel address bit (CAB) of the connection memory defines the source
information(streamandchannel)ofthetime-slotthatwillbeswitchedtotheoutput
from data memory.
The
V/C(Variable/ConstantDelay)bitineachconnectionmemorylocation
allows the per-channel selection between variable and constant throughput
delay modes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., RX n channel m data comes from the
TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.
INITIALIZATION O. THE IDT7290820
After power up, the state of the connection memory is unknown. As such,
theoutputsshouldbeputinhighimpedancebyholdingtheODElow. Whilethe
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.
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