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參數(shù)資料
| 型號： | IDT72T18115L6-7BBI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS |
| 中文描述： | 2.5伏高速TeraSync先進先出18-BIT/9-BIT配置 |
| 文件頁數(shù)： | 23/55頁 |
| 文件大?。?/td> | 540K |
| 代理商： | IDT72T18115L6-7BBI |
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23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D
0
- D
n
)
Data inputs for 18-bit wide data (D
0
- D
17
) or data inputs for 9-bit wide data
(D
0
- D
8
).
CONTROLS:
MASTER RESET
(
MRS
)
A Master Reset is accomplished whenever the
MRS
input is taken to a LOW
state. This operation sets the internal read and write pointers to the first location
of the RAMarray.
PAE
will go LOW,
PAF
will go HIGH, and
HF
will go HIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with
EF
and
FF
are selected.
EF
will go LOW and
FF
will go HIGH. If
FWFT/SI is HIGH, then the First Word Fall Through mode (FWFT), along with
IR
and
OR
, are selected.
OR
will go HIGH and
IR
will go LOW.
All control settings such as OW, IW,
BE
, RM PFMand IP are defined during
the Master Reset cycle.
During a Master Reset, the output register is initialized to all zeroes. A Master
Reset is required after power up, before a write operation can take place.
MRS
is asynchronous.
See Figure 9,
Master Reset Timng
, for the relevant timng diagram
PARTIAL RESET (
PRS
)
A Partial Reset is accomplished whenever the
PRS
input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAMarray,
PAE
goes LOW,
PAF
goes HIGH,
and
HF
goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then
FF
will go HIGH and
EF
will go LOW. If the First Word
Fall Through mode is active, then
OR
will go HIGH, and
IR
will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programmng method (parallel or serial) currently active at
the time of Partial Reset is also retained. The output register is initialized to all
zeroes.
PRS
is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogrammng programmable flag offset settings may not be
convenient.
See Figure 10,
Partial Reset Timng
, for the relevant timng diagram
ASYNCHRONOUS WRITE (
ASYW
)
The write port can be configured for either Synchronous or Asynchronous
mode of operation. If during Master Reset the
ASYW
input is LOW, then
Asynchronous operation of the write port will be selected. During Asynchro-
nous operation of the write port the WCLK input becomes WR input, this is the
Asynchronous write strobe input. A rising edge on WR will write data present
on the Dn inputs into the FIFO. (
WEN
must be tied LOW when using the write
port in Asynchronous mode).
When the write port is configured for Asynchronous operation the full flag
(
FF
) operates in an asynchronous manner, that is, the full flag will be updated
based in both a write operation and read operation. Note, if Asynchronous
mode is selected, FWFT is not permssable. Refer to Figures 30, 31, 34 and
35 for relevant timng and operational waveforms.
ASYNCHRONOUS READ (
ASYR
)
The read port can be configured for either Synchronous or Asynchronous
mode of operation. If during a Master Reset the
ASYR
input is LOW, then
Asynchronous operation of the read port will be selected. During Asynchro-
nous operation of the read port the RCLK input becomes RD input, this is the
Asynchronous read strobe input. A rising edge on RD will read data fromthe
FIFO via the output register and Qn port. (
REN
must be tied LOW during
Asynchronous operation of the read port).
The
OE
input provides three-state control of the Qn output bus, in an
asynchronous manner. (
RCS
, provides three-state control of the read port in
Synchronous mode).
When the read port is configured for Asynchronous operation the device
must be operating on IDT standard mode, FWFT mode is not permssible if the
read port is Asynchronous. The Empty Flag (
EF
) operates in an Asynchronous
manner, that is, the empty flag will be updated based on both a read operation
and a write operation. Refer to Figures 32, 33, 34 and 35 for relevant timng
and operational waveforms.
RETRANSMIT (
RT
)
The Retransmt (
RT
) input is used in conjunction with the MARK input,
together they provide a means by which data previously read out of the FIFO
can be reread any number of times. If retransmt operation has been selected
(i.e. the MARK input is HIGH), a rising edge on RCLK while
RT
is LOW will reset
the read pointer back to the memory location set by the user via the MARK input.
If IDT standard mode has been selected the
EF
flag will go LOW and remain
LOW for the time that
RT
is held LOW.
RT
can be held LOW for any number
of RCLK cycles, the read pointer being reset to the marked location. The next
rising edge of RCLK after
RT
has returned HIGH, will cause
EF
to go HIGH,
allowing read operations to be performed on the FIFO. The next read operation
will access data fromthe marked memory location.
Subsequent retransmt operations may be performed, each time the read
pointer returning to the marked location. See Figure 18,
Retransmt fromMark
(IDT Standard mode)
for the relevant timng diagram
If FWFT mode has been selected the
OR
flag will go HIGH and remain HIGH
for the time that
RT
is held LOW.
RT
can be held LOW for any number of RCLK
cycles, the read pointer being reset to the marked location. The next RCLK
rising edge after
RT
has returned HIGH, will cause
OR
to go LOW and due to
FWFT operation, the contents of the marked memory location will be loaded onto
the output register, a read operation being required for all subsequent data
reads.
Subsequent retransmt operations may be performed each time the read
pointer returning to the marked location. See Figure 19,
Retransmt fromMark
(FWFT mode)
for the relevant timng diagram
MARK
The MARK input is used to select Retransmt mode of operation. An RCLK
rising edge while MARK is HIGH will mark the memory location of the data
currently present on the output register, the device will also be placed into
retransmt mode. Note, for the IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895 there must be a mnimumof 32 bytes of data between the
write pointer and read pointer when the MARK is asserted, for the IDT72T18105/
72T18115 there must be a mnimumof 128 bytes and for the IDT72T18125
there must be a mnimumof 256 bytes. Remember, 2(x9) bytes = 1(x18) word.
(32 bytes = 16 word = 8 long words). Also, once the MARK is set, the write
pointer will not increment past the “marked” location until the MARK is
deasserted. This prevents “overwriting” of retransmt data.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T18125L10BB | 功能描述:IC FIFO 524X18 2.5V 10NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:90 系列:74ABT 功能:同步，雙端口 存儲容量:4.6K（64 x 36 x2） 數(shù)據(jù)速率:67MHz 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:120-HLQFP（14x14） 包裝:托盤 產(chǎn)品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984 |
| IDT72T18125L4-4BB | 功能描述:IC FIFO 524X18 2.5V 4NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T18125L4-4BBG | 功能描述:IC FIFO 524X18 2.5V 4NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:90 系列:74ABT 功能:同步，雙端口 存儲容量:4.6K（64 x 36 x2） 數(shù)據(jù)速率:67MHz 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:120-HLQFP（14x14） 包裝:托盤 產(chǎn)品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984 |
| IDT72T18125L5BB | 功能描述:IC FIFO 524X18 2.5V 5NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T18125L5BBGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 524X18 2.5V 5NS 240BGA |
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