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參數(shù)資料
| 型號： | IDT72T18115L6-7BBI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS |
| 中文描述： | 2.5伏高速TeraSync先進先出18-BIT/9-BIT配置 |
| 文件頁數(shù)： | 45/55頁 |
| 文件大小： | 540K |
| 代理商： | IDT72T18115L6-7BBI |
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45
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
NOTES:
1. m=
PAF
offset .
2. D = maximumFIFO depth.
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 2,048 for the IDT72T1845, 4,096 for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the IDT72T1875,
32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,096 for the IDT72T1845, 8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875, 65,536 for the IDT72T1885,
131,072 for the IDT72T1895, 262,144 for the IDT72T18105, 524,288 for the IDT72T18115 and 1,048,576 for the IDT72T18125.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 2,049 for the IDT72T1845, 4,097 for the IDT72T1855, 8,193 for the IDT72T1865, 16,385 for the IDT72T1875,
32,769 for the IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105, 262,145 for the IDT72T18115 and 524,289 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,097 for the IDT72T1845, 8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the IDT72T1875, 65,537 for the IDT72T1885,
131,073 for the IDT72T1895, 262,145 for the IDT72T18105, 524,289 for the IDT72T18115 and 1,048,577 for the IDT72T18125.
3. t
SKEW2
is the mnimumtime between a rising RCLK edge and a rising WCLK edge to guarantee that
PAF
will go HIGH (after one WCLK cycle plus t
PAFS
). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW2
, then the
PAF
deassertion time may be delayed one extra WCLK cycle.
4.
PAF
is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFMHIGH during Master Reset.
6.
RCS
is LOW.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAF
RCLK
REN
5909 drw27
1
2
1
2
D-(m+1) words
in FIFO
(2)
D - m words in FIFO
(2)
D - (m +1) words in FIFO
(2)
t
ENH
t
ENS
t
PAFS
t
ENS
t
ENH
t
CLKL
t
SKEW2
(3)
t
PAFS
t
CLKL
NOTES:
1. n =
PAE
offset.
2. For IDT Standard mode
3. For FWFT mode.
4.
t
SKEW2
is the mnimumtime between a rising WCLK edge and a rising RCLK edge to guarantee that
PAE
will go HIGH (after one RCLK cycle plus t
PAES
). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
, then the
PAE
deassertion may be delayed one extra RCLK cycle.
5.
PAE
is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFMHIGH during Master Reset.
7.
RCS
= LOW.
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAE
RCLK
1
2
1
2
REN
5909 drw28
n + 1 words in FIFO
(2)
,
n + 2 words in FIFO
(3)
t
ENS
t
SKEW2
(4)
t
ENH
t
PAES
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
t
PAES
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
t
ENS
t
ENH
t
CLKH
t
CLKL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T18125L6-7BBI | 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS |
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| IDT72T2098L4BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T2098L5BB | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T2098L5BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T18125L10BB | 功能描述:IC FIFO 524X18 2.5V 10NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:74ABT 功能:同步，雙端口 存儲容量:4.6K（64 x 36 x2） 數(shù)據(jù)速率:67MHz 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:120-HLQFP（14x14） 包裝:托盤 產(chǎn)品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984 |
| IDT72T18125L4-4BB | 功能描述:IC FIFO 524X18 2.5V 4NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T18125L4-4BBG | 功能描述:IC FIFO 524X18 2.5V 4NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:74ABT 功能:同步，雙端口 存儲容量:4.6K（64 x 36 x2） 數(shù)據(jù)速率:67MHz 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:120-HLQFP（14x14） 包裝:托盤 產(chǎn)品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984 |
| IDT72T18125L5BB | 功能描述:IC FIFO 524X18 2.5V 5NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T18125L5BBGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 524X18 2.5V 5NS 240BGA |
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