參數(shù)資料
型號(hào)： IDT72T1875L6-7BBI
廠商： Integrated Device Technology, Inc.
英文描述： 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
中文描述： 2.5伏高速TeraSync先進(jìn)先出18-BIT/9-BIT配置
文件頁(yè)數(shù)： 26/55頁(yè)
文件大小： 540K
代理商： IDT72T1875L6-7BBI
26
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
programmng of the offsets. (D
8
becomes a valid bit). Additionally, output Q
8
will
become a valid bit when performng a read of the offset register. IP mode is
selected during Master Reset by the state of the IP input pin.
OUTPUTS:
FULL FLAG (
FF
/
IR
)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (
FF
) function
is selected. When the FIFO is full,
FF
will go LOW, inhibiting further write
operations. When
FF
is HIGH, the FIFO is not full. If no reads are performed
after a reset (either
MRS
or
PRS
),
FF
will go LOW after D writes to the FIFO.
If x18 Input or x18 Output bus Width is selected, D = 2,048 for the IDT72T1845,
4,096 for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the
IDT72T1875, 32,768 for the IDT72T1885, 65,536 for the IDT72T1895,
131,072 writes for the IDT72T18105, 262,144 writes for the IDT72T18115 and
524,288 writes for the IDT72T18125. If both x9 Input and x9 Output bus Widths
are selected, D = 4,096 for the IDT72T1845, 8,192 for the IDT72T1855,
16,384 for the IDT72T1865, 32,768 for the IDT72T1875, 65,536 for the
IDT72T1885, 131,072 for the IDT72T1895, 262,144 writes for the
IDT72T18105, 524,288 writes for the IDT72T18115 and 1,048,576 writes for
the IDT72T18125. See Figure 11,
Write Cycle and Full Flag Timng (IDT
Standard Mode)
, for the relevant timng information.
In FWFT mode, the Input Ready (
IR
) function is selected.
IR
goes LOW
when memory space is available for writing in data. When there is no longer
any free space left,
IR
goes HIGH, inhibiting further write operations. If no reads
are performed after a reset (either
MRS
or
PRS
),
IR
will go HIGH after D writes
to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 2,049 for the
IDT72T1845, 4,097 for the IDT72T1855, 8,193 for the IDT72T1865, 16,385
for the IDT72T1875, 32,769 for the IDT72T1885, 65,537 for the IDT72T1895,
131,073 writes for the IDT72T18105, 262,145 writes for the IDT72T18115 and
524,289 writes for the IDT72T18125. If both x9 Input and x9 Output bus Widths
are selected, D = 4,097 for the IDT72T1845, 8,193 for the IDT72T1855, 16,385
for the IDT72T1865, 32,769 for the IDT72T1875, 65,537 for the IDT72T1885,
131,073 for the IDT72T1895, 262,145 writes for the IDT72T18105, 524,289
writes for the IDT72T18115 and 1,048,577 writes for the IDT72T18125. See
Figure 14,
Write Timng (FWFT Mode)
, for the relevant timng information.
The
IR
status not only measures the contents of the FIFO memory, but also
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert
IR
is one greater than needed to
assert
FF
in IDT Standard mode.
FF
/
IR
is synchronous and updated on the rising edge of WCLK.
FF
/
IR
are
double register-buffered outputs.
Note, when the device is in Retransmt mode, this flag is a comparison of the
write pointer to the marked location. This differs fromnormal mode where this
flag is a comparison of the write pointer to the read pointer.
EMPTY FLAG (
EF
/
OR
)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (
EF
)
function is selected. When the FIFO is empty,
EF
will go LOW, inhibiting further
read operations. When
EF
is HIGH, the FIFO is not empty. See Figure 12,
Read
Cycle, Empty Flag and First Word Latency Timng (IDT Standard Mode)
, for
the relevant timng information.
In FWFT mode, the Output Ready (
OR
) function is selected.
OR
goes LOW
at the same time that the first word written to an empty FIFO appears valid on
the outputs.
OR
stays LOW after the RCLK LOW to HIGH transition that shifts the
last word fromthe FIFO memory to the outputs.
OR
goes HIGH only with a true
read (RCLK with
REN
= LOW). The previous data stays at the outputs, indicating
the last word was read. Further data reads are inhibited until
OR
goes LOW
again. See Figure 15,
Read Timng (FWFT Mode)
, for the relevant timng
information.
EF
/
OR
is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF
is a double register-buffered output. In FWFT
mode,
OR
is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF
)
The Programmable Almost-Full flag (
PAF
) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS
),
PAF
will go LOW after (D-m words are written
to the FIFO.
If x18 Input or x18 Output bus Width is selected, (D-m = (2,048-m
writes for the IDT72T1845, (4,096-m writes for the IDT72T1855, (8,192-m
writes for the IDT72T1865, (16,384-m writes for the IDT72T1875, (32,768-m
writes for the IDT72T1885, (65,536-m writes for the IDT72T1895, (131,072-m
writes for the IDT72T18105, (262,144-m writes for the IDT72T18115 and
(524,288-m writes for the IDT72T18125. If both x9 Input and x9 Output bus
Widths are selected, (D-m = (4,096-m writes for the IDT72T1845, (8,192-m
writes for the IDT72T1855, (16,384-m writes for the IDT72T1865, (32,768-m
writes for the IDT72T1875, (65,536-m writes for the IDT72T1885, (131,072-m
writes for the IDT72T1895, (262,144-m writes for the IDT72T18105,
(524,288-m writes for the IDT72T18115 and (1,048,576-m writes for the
IDT72T18125. The offset “m” is the full offset value. The default setting for this
value is stated in Table 2.
In FWFT mode, if x18 Input or x18 Output bus Width is selected, the
PAF
will go LOW after (2,049-m writes for the IDT72T1845, (4,097-m writes for the
IDT72T1855, (8,193-m writes for the IDT72T1865, (16,385-m writes for the
IDT72T1875, (32,769-m writes for the IDT72T1885, (65,537-m writes for the
IDT72T1895, (131,073-m writes for the IDT72T18105, (262,145-m writes
for the IDT72T18115 and (524,289-m writes for the IDT72T18125. If both x9
Input and x9 Output bus Widths are selected, the
PAF
will go LOW after (4,097-
m writes for the IDT72T1845, (8,193-m writes for the IDT72T1855, (16,385-m
writes for the IDT72T1865, (32,769-m writes for the IDT72T1875, (65,537-m
writes for the IDT72T1885, (131,073-m writes for the IDT72T1895, (262,145-
m writes for the IDT72T18105, (524,289-m writes for the IDT72T18115
and (1,048,577-m writes for the IDT72T18125. The offset mis the full offset
value. The default setting for this value is stated in Table 2.
See Figure 23,
Synchronous Programmable Almost-Full Flag Timng (IDT
Standard and FWFT Mode)
, for the relevant timng information.
If asynchronous
PAF
configuration is selected, the
PAF
is asserted LOW
on the LOW-to-HIGH transition of the Write Clock (WCLK).
PAF
is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous
PAF
configuration is selected, the
PAF
is updated on the rising edge of WCLK. See
Figure 25 for
Asynchronous Programmable Almost-Full Flag Timng (IDT
Standard and FWFT Mode).
Note, when the device is in Retransmt mode, this flag is a comparison of the
write pointer to the marked location. This differs fromnormal mode where this
flag is a comparison of the write pointer to the read pointer.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE
)
The Programmable Almost-Empty flag (
PAE
) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in Table 2.
In FWFT mode, the
PAE
will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in Table 2.
See Figure 24,
Synchronous Programmable Almost-Empty Flag Timng
(IDT Standard and FWFT Mode)
, for the relevant timng information.
相關(guān)PDF資料
PDF描述
IDT72T18105L6-7BBI 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
IDT72T18115L6-7BBI 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
IDT72T18125L6-7BBI 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
IDT72T20108 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T2098L4BBI 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
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